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| author | Ruben Undheim <ruben.undheim@gmail.com> | 2018-10-13 20:34:44 +0200 |
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| committer | Ruben Undheim <ruben.undheim@gmail.com> | 2018-10-13 20:34:44 +0200 |
| commit | c50afc4246d552db079aec303b0d79ae92107a67 (patch) | |
| tree | 546271de9e8e4f61697785d0687ab289152ac6ca /.travis.yml | |
| parent | a36d1701dd99736b82f64ed870e7464f2deae220 (diff) | |
| download | yosys-c50afc4246d552db079aec303b0d79ae92107a67.tar.gz yosys-c50afc4246d552db079aec303b0d79ae92107a67.tar.bz2 yosys-c50afc4246d552db079aec303b0d79ae92107a67.zip | |
Documentation improvements etc.
- Mention new feature in the SystemVerilog section in the README file
- Commented changes much better
- Rename a few signals to make it clearer
- Prevent warning for unused signals in an easier way
- Add myself as copyright holder to 2 files
- Fix one potential memory leak (delete 'wire' if not in modport)
Diffstat (limited to '.travis.yml')
0 files changed, 0 insertions, 0 deletions