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| author | Clifford Wolf <clifford@clifford.at> | 2019-04-22 09:35:14 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2019-04-23 21:36:59 +0200 |
| commit | 0bf9d0087c43f9db3d56cb2bed17268def21eb67 (patch) | |
| tree | d9186950668b1bbf196a9d0b38ba0aa7954ae505 /.travis.yml | |
| parent | aec2475a9d7a2a903d5015840a3320ce2cedf5cd (diff) | |
| download | yosys-0bf9d0087c43f9db3d56cb2bed17268def21eb67.tar.gz yosys-0bf9d0087c43f9db3d56cb2bed17268def21eb67.tar.bz2 yosys-0bf9d0087c43f9db3d56cb2bed17268def21eb67.zip | |
Add support for $assert/$assume/$cover to write_verilog
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to '.travis.yml')
0 files changed, 0 insertions, 0 deletions