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| author | Clifford Wolf <clifford@clifford.at> | 2019-05-25 19:17:05 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-05-25 19:17:05 +0200 |
| commit | a90eec12c96cd58d2807bd15e7331d987ecaa4bb (patch) | |
| tree | cae7f9eb9e961c8143f0c1d601f8bc461140a559 /.gitignore | |
| parent | b7dd7c2dcd8e3e9b10407799f2978872a80f1860 (diff) | |
| parent | 6352df42ae3f41880c309d00df2db2eba9126d42 (diff) | |
| download | yosys-a90eec12c96cd58d2807bd15e7331d987ecaa4bb.tar.gz yosys-a90eec12c96cd58d2807bd15e7331d987ecaa4bb.tar.bz2 yosys-a90eec12c96cd58d2807bd15e7331d987ecaa4bb.zip | |
Merge pull request #1041 from YosysHQ/clifford/fix1040
Fix handling of offset and upto module ports in write_blif
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