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| author | Kaj Tuomi <kaj.tuomi@siru.fi> | 2019-05-18 14:20:30 +0300 |
|---|---|---|
| committer | Kaj Tuomi <kaj.tuomi@siru.fi> | 2019-05-18 14:20:30 +0300 |
| commit | 48ddbe52fb1428fc8f7f3d6444c5637eb151475f (patch) | |
| tree | 64bdc5903bf099d59aa9ba9dacff03d8b7a9eda2 /.github | |
| parent | b6345b111d994ff0de1bcd91379db1c289feb03b (diff) | |
| download | yosys-48ddbe52fb1428fc8f7f3d6444c5637eb151475f.tar.gz yosys-48ddbe52fb1428fc8f7f3d6444c5637eb151475f.tar.bz2 yosys-48ddbe52fb1428fc8f7f3d6444c5637eb151475f.zip | |
Read bigger Verilog files.
Hit parser limit with 3M gate design. This commit fix it.
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