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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-12 08:49:15 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-12 08:49:15 -0700 |
| commit | 1e838a8913afa36a57d425f26ea881f5071b8b5d (patch) | |
| tree | c46b5e6f6f0f94a55f6601193f98b3ca9d83ff50 /.github | |
| parent | 4c9fde87d170fc8d4b729581b055407553951e4c (diff) | |
| download | yosys-1e838a8913afa36a57d425f26ea881f5071b8b5d.tar.gz yosys-1e838a8913afa36a57d425f26ea881f5071b8b5d.tar.bz2 yosys-1e838a8913afa36a57d425f26ea881f5071b8b5d.zip | |
Retry "Add "-W' wire delay arg to abc9, use from synth_xilinx"
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