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| author | Zachary Snow <zach@zachjs.com> | 2020-12-18 12:59:08 -0700 |
|---|---|---|
| committer | Zachary Snow <zach@zachjs.com> | 2020-12-18 20:33:14 -0700 |
| commit | 0d8e5d965f2585e6ed151a9e92d83ee63df6172a (patch) | |
| tree | f2da85bd5aaf90406d3536b64749837d44003eab /.github | |
| parent | 40e35993af6ecb6207f15cc176455ff8d66bcc69 (diff) | |
| download | yosys-0d8e5d965f2585e6ed151a9e92d83ee63df6172a.tar.gz yosys-0d8e5d965f2585e6ed151a9e92d83ee63df6172a.tar.bz2 yosys-0d8e5d965f2585e6ed151a9e92d83ee63df6172a.zip | |
Sign extend port connections where necessary
- Signed cell outputs are sign extended when bound to larger wires
- Signed connections are sign extended when bound to larger cell inputs
- Sign extension is performed in hierarchy and flatten phases
- genrtlil indirects signed constants through signed wires
- Other phases producing RTLIL may need to be updated to preserve
signedness information
- Resolves #1418
- Resolves #2265
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