generic/examples/blinky.v


1
2
3
4
5
6
7
8
9
10
11
12

module top(input clk, rst, output reg [7:0] leds);

reg [7:0] ctr;
always @(posedge clk)
	if (rst)
		ctr <= 8'h00;
	else
		ctr <= ctr + 1'b1;

assign leds = ctr;

endmodule