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yosys -import
read_verilog $::env(SOURCES)
synth_xilinx -nolutram -nowidelut -nosrl -nocarry -nodsp
techmap -map ../remap.v
# opt_expr -undriven makes sure all nets are driven, if only by the $undef
# net.
opt_expr -undriven
opt_clean
setundef -zero -params
write_json $::env(OUT_JSON)
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