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/*
* nextpnr -- Next Generation Place and Route
*
* Copyright (C) 2021 Symbiflow Authors
*
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
#ifndef NEXTPNR_H
#error Include "dedicated_interconnect.h" via "nextpnr.h" only.
#endif
NEXTPNR_NAMESPACE_BEGIN
struct TileTypeBelPin {
int32_t tile_type;
int32_t bel_index;
IdString bel_pin;
bool operator < (const TileTypeBelPin &other) const {
if(tile_type >= other.tile_type) {
return false;
}
if(bel_index >= other.bel_index) {
return false;
}
return bel_pin < other.bel_pin;
}
bool operator ==(const TileTypeBelPin &other) const {
return tile_type == other.tile_type && bel_index == other.bel_index && bel_pin == other.bel_pin;
}
bool operator !=(const TileTypeBelPin &other) const {
return tile_type != other.tile_type || bel_index != other.bel_index || bel_pin != other.bel_pin;
}
};
struct DeltaTileTypeBelPin {
int32_t delta_x;
int32_t delta_y;
TileTypeBelPin type_bel_pin;
bool operator ==(const DeltaTileTypeBelPin &other) const {
return delta_x == other.delta_x && delta_y == other.delta_y && type_bel_pin == other.type_bel_pin;
}
bool operator !=(const DeltaTileTypeBelPin &other) const {
return delta_x != other.delta_x || delta_y != other.delta_y || type_bel_pin != other.type_bel_pin;
}
};
NEXTPNR_NAMESPACE_END
template <> struct std::hash<NEXTPNR_NAMESPACE_PREFIX TileTypeBelPin>
{
std::size_t operator()(const NEXTPNR_NAMESPACE_PREFIX TileTypeBelPin &type_bel_pin) const noexcept
{
std::size_t seed = 0;
boost::hash_combine(seed, std::hash<int32_t>()(type_bel_pin.tile_type));
boost::hash_combine(seed, std::hash<int32_t>()(type_bel_pin.bel_index));
boost::hash_combine(seed, std::hash<NEXTPNR_NAMESPACE_PREFIX IdString>()(type_bel_pin.bel_pin));
return seed;
}
};
template <> struct std::hash<NEXTPNR_NAMESPACE_PREFIX DeltaTileTypeBelPin>
{
std::size_t operator()(const NEXTPNR_NAMESPACE_PREFIX DeltaTileTypeBelPin &delta_bel_pin) const noexcept
{
std::size_t seed = 0;
boost::hash_combine(seed, std::hash<int32_t>()(delta_bel_pin.delta_x));
boost::hash_combine(seed, std::hash<int32_t>()(delta_bel_pin.delta_y));
boost::hash_combine(seed, std::hash<NEXTPNR_NAMESPACE_PREFIX TileTypeBelPin>()(delta_bel_pin.type_bel_pin));
return seed;
}
};
NEXTPNR_NAMESPACE_BEGIN
struct Context;
// This class models dedicated interconnect present in the given fabric.
//
// Examples of dedicate interconnect:
// - IBUF.O -> ISERDES.I
// - IBUF.O -> IDELAY.I
// - CARRY4.CO[3] -> CARRY4.CIN
//
// Note that CARRY4.CYINIT does not **require** dedicated interconnect, so
// it doesn't qualify.
//
// This class discovers dedicated interconnect by examing the routing graph.
// This discovery make be expensive, and require caching to accelerate
// startup.
struct DedicatedInterconnect {
const Context *ctx;
std::unordered_map<TileTypeBelPin, std::unordered_set<DeltaTileTypeBelPin>> pins_with_dedicate_interconnect;
void init(const Context *ctx);
// Is this BEL placed in a location that is valid based on dedicated
// interconnect?
//
// Note: Only BEL pin sinks are checked.
bool isBelLocationValid(BelId bel, const CellInfo* cell) const;
void find_dedicated_interconnect();
void print_dedicated_interconnect() const;
bool check_routing(
BelId src_bel, IdString src_bel_pin,
BelId dst_bel, IdString dst_bel_pin) const;
void expand_bel(BelId bel, IdString pin, WireId wire);
};
NEXTPNR_NAMESPACE_END
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