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#!/usr/bin/env python
#
# Copyright 2008 Google Inc. All Rights Reserved.
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
#      http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.

"""Driver for starting up Google Mock class generator."""

__author__ = 'nnorwitz@google.com (Neal Norwitz)'

import os
import sys

if __name__ == '__main__':
  # Add the directory of this script to the path so we can import gmock_class.
  sys.path.append(os.path.dirname(__file__))

  from cpp import gmock_class
  # Fix the docstring in case they require the usage.
  gmock_class.__doc__ = gmock_class.__doc__.replace('gmock_class.py', __file__)
  gmock_class.main()
">localparam WORD = (DATA_WIDTH-1); localparam DEPTH = (2**ADDRESS_WIDTH-1); reg [WORD:0] data_out_r; reg [WORD:0] memory [0:DEPTH]; always @(posedge clk) begin if (write_enable) memory[address_in] <= data_in; data_out_r <= memory[address_in]; end assign data_out = data_out_r; endmodule // block_ram `default_nettype none module distributed_ram #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=4) (input wire write_enable, clk, input wire [DATA_WIDTH-1:0] data_in, input wire [ADDRESS_WIDTH-1:0] address_in, output wire [DATA_WIDTH-1:0] data_out); localparam WORD = (DATA_WIDTH-1); localparam DEPTH = (2**ADDRESS_WIDTH-1); reg [WORD:0] data_out_r; reg [WORD:0] memory [0:DEPTH]; always @(posedge clk) begin if (write_enable) memory[address_in] <= data_in; data_out_r <= memory[address_in]; end assign data_out = data_out_r; endmodule // distributed_ram `default_nettype none module distributed_ram_manual #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=4) (input wire write_enable, clk, input wire [DATA_WIDTH-1:0] data_in, input wire [ADDRESS_WIDTH-1:0] address_in, output wire [DATA_WIDTH-1:0] data_out); localparam WORD = (DATA_WIDTH-1); localparam DEPTH = (2**ADDRESS_WIDTH-1); reg [WORD:0] data_out_r; (* ram_style = "block" *) reg [WORD:0] memory [0:DEPTH]; always @(posedge clk) begin if (write_enable) memory[address_in] <= data_in; data_out_r <= memory[address_in]; end assign data_out = data_out_r; endmodule // distributed_ram `default_nettype none module distributed_ram_manual_syn #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=4) (input wire write_enable, clk, input wire [DATA_WIDTH-1:0] data_in, input wire [ADDRESS_WIDTH-1:0] address_in, output wire [DATA_WIDTH-1:0] data_out); localparam WORD = (DATA_WIDTH-1); localparam DEPTH = (2**ADDRESS_WIDTH-1); reg [WORD:0] data_out_r; (* synthesis, ram_block *) reg [WORD:0] memory [0:DEPTH]; always @(posedge clk) begin if (write_enable) memory[address_in] <= data_in; data_out_r <= memory[address_in]; end assign data_out = data_out_r; endmodule // distributed_ram