3rdparty/QtPropertyBrowser/src/QtDatePropertyManager


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/* -*-  Mode:C; c-basic-offset:4; tab-width:4; indent-tabs-mode:nil -*- */
/*
 * vmmu.h: virtual memory management unit related APIs and data structure.
 * Copyright (c) 2004, Intel Corporation.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
 * Place - Suite 330, Boston, MA 02111-1307 USA.
 *
 *  Yaozu Dong (Eddie Dong) (Eddie.dong@intel.com)
 */

#ifndef XEN_TLBthash_H
#define XEN_TLBthash_H

#include <xen/config.h>
#include <xen/types.h>
#include <public/xen.h>
#include <asm/tlb.h>
#include <asm/regionreg.h>

//#define         THASH_TLB_TR            0
//#define         THASH_TLB_TC            1


// bit definition of TR, TC search cmobination
//#define         THASH_SECTION_TR        (1<<0)
//#define         THASH_SECTION_TC        (1<<1)

/*
 * Next bit definition must be same with THASH_TLB_XX
 */
typedef union search_section {
        struct {
                u32 tr : 1;
                u32 tc : 1;
                u32 rsv: 30;
        };
        u32     v;
} search_section_t;

#define         MAX_CCN_DEPTH           4       // collision chain depth
#define         VCPU_TLB_SHIFT          (22)
#define         VCPU_TLB_SIZE           (1UL<<VCPU_TLB_SHIFT)
#define         VCPU_TLB_ORDER          VCPU_TLB_SHIFT - PAGE_SHIFT
#define         PTA_BASE_SHIFT          (15)

#ifndef __ASSEMBLY__
#define HIGH_32BITS(x)  bits(x,32,63)
#define LOW_32BITS(x)   bits(x,0,31)

typedef enum {
        ISIDE_TLB=0,
        DSIDE_TLB=1
} CACHE_LINE_TYPE;

typedef struct thash_data {
    union {
        struct {
            u64 p    :  1; // 0
            u64 rv1  :  1; // 1
            u64 ma   :  3; // 2-4
            u64 a    :  1; // 5
            u64 d    :  1; // 6
            u64 pl   :  2; // 7-8
            u64 ar   :  3; // 9-11
            u64 ppn  : 38; // 12-49
            u64 rv2  :  2; // 50-51
            u64 ed   :  1; // 52
            u64 ig1  :  11; //53-63
        };
        struct {
            u64 __rv1 : 53;	// 0-52
            // next extension to ig1, only for TLB instance
            u64 tc : 1;     // 53 TR or TC
            u64 locked  : 1;	// 54 entry locked or not
            CACHE_LINE_TYPE cl : 1; // I side or D side cache line
            u64 nomap : 1;   // entry cann't be inserted into machine TLB.
            u64 __ig1  :  5; // 56-61
            u64 checked : 1; // for VTLB/VHPT sanity check
            u64 invalid : 1; // invalid entry
        };
        u64 page_flags;
    };                  // same for VHPT and TLB

    union {
        struct {
            u64 rv3  :  2; // 0-1
            u64 ps   :  6; // 2-7
            u64 key  : 24; // 8-31
            u64 rv4  : 32; // 32-63
        };
        struct {
            u64 __rv3  : 32; // 0-31
            // next extension to rv4
            u64 rid  : 24;  // 32-55
            u64 __rv4  : 8; // 56-63
        };
        u64 itir;
    };
    union {
        struct {        // For TLB
            u64 ig2  :  12; // 0-11
            u64 vpn  :  49; // 12-60
            u64 vrn  :   3; // 61-63
        };
        u64 vadr;
        u64 ifa;
        struct {        // For VHPT
            u64 tag  :  63; // 0-62