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* nexus: Check IO-bank compatibilitygatecat2023-02-211-0/+10
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Add missing <set> includesgatecat2023-01-201-0/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* nexus: Transform registered output parametersDavid Lattimore2022-10-051-0/+4
| | | | | | | | | | | | Dual ported: OUTREG_A -> OUT_REGMODE_A OUTREG_B -> OUT_REGMODE_B Pseudo dual ported: OUTREG -> OUT_REGMODE_B Single ported: OUTREG -> OUT_REGMODE_A
* refactor: Use IdString::in instead of || chainsgatecat2022-08-101-2/+2
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* nexus: Add timing data for LRAMgatecat2022-08-101-0/+13
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* refactor: id(stringf(...)) to new idf(...) helpergatecat2022-08-101-27/+24
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* nexus: Fix CSDECODE parsinggatecat2022-07-191-1/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* clangformatgatecat2022-03-311-3/+2
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Rename parse_lattice_param to parse_lattice_param_from_cellMaciej Dudek2022-03-301-18/+22
| | | | | | | | | Add new definition for parse_lattice_param Now parse_lattice_param is design to parse Property rather than search for it in cell. This functionalty was move to parse_lattice_param_from_cell. Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
* clangformatgatecat2022-03-171-2/+2
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* nexus: Corrected auto frequency constraint for LF output of OSCAMaciej Kurc2022-03-161-2/+2
| | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
* nexus: Added support for the DCS BelMaciej Kurc2022-03-161-2/+23
| | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
* clangformatgatecat2022-03-091-1/+2
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* nexus: DCCs cannot be cascadedMaciej Dudek2022-03-091-1/+1
| | | | | | This commit solves implicit cascading when clock signal drives DCC and logic Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
* Switch to potentially-sparse net users arraygatecat2022-02-271-20/+23
| | | | | | | | This uses a new data structure for net.users that allows gaps, so removing a port from a net is no longer an O(n) operation on the number of users the net has. Signed-off-by: gatecat <gatecat@ds0.me>
* refactor: New member functions to replace design_utilsgatecat2022-02-181-155/+155
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* refactor: Use constids instead of id("..")gatecat2022-02-161-20/+20
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* nexus: reduce OSCA worst case to 7%Dan Callaghan2022-02-101-1/+1
| | | | | | | | | | | The current version of Crosslink-NX Family Data Sheet lists the high frequency oscillator maximum frequency as 481.5MHz (that is, 7% higher than its nominal 450MHz): https://www.latticesemi.com/-/media/LatticeSemi/Documents/DataSheets/CrossLink/FPGA-DS-02049-1-2-1-CrossLink-NX-Family.ashx?document_id=52780 Older documents listed a wider frequency range but ±7% is the range for production parts.
* Fixed correction of Nexus OSCA frequency constraintsMaciej Kurc2022-02-021-2/+2
| | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
* Added honoring OSCA output frequency tolerance during constraints generationMaciej Kurc2022-01-281-2/+3
| | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
* Removed the need for MULT36_CORE bel for implementing the MULTADDSUB9X9WIDE ↵Maciej Kurc2022-01-251-1/+1
| | | | | | macro Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
* clangformatgatecat2021-12-121-15/+11
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Added checking if all FFs added to an existing cluster have matching ↵Maciej Kurc2021-11-231-0/+44
| | | | | | configuration Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
* Fixed potential issues with carry-chain cluster expansion, added a parameter ↵Maciej Kurc2021-11-221-14/+15
| | | | | | controlling the ratio of FFs that got glued to carry-chain clusters. Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
* Added appending FFs to other existing LUT cluster types (carry, widefn)Maciej Kurc2021-11-221-18/+67
| | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
* Added an option to control LUT and FF packingMaciej Kurc2021-11-221-1/+5
| | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
* Added clustering free LUTs and FFsMaciej Kurc2021-11-221-0/+73
| | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
* nexus: Fix DSP macro placementgatecat2021-09-221-32/+32
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Added support for syn_useioff for enabling tri-state control FF integration ↵Maciej Kurc2021-09-201-13/+23
| | | | | | into IOLOGIC. Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
* Use correct names for IDDRX1_ODDRX1 FASM featuresMaciej Kurc2021-09-171-17/+3
| | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
* Added automatic inference and integration of FFs driving T pin into IOLOGICMaciej Kurc2021-09-171-16/+171
| | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
* Added handling of the case when tri-state control net bypasses SIOLOGIC belMaciej Kurc2021-09-171-2/+81
| | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
* nexus: Basic packer and FASM support for I/ODDRgatecat2021-07-281-0/+87
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Fixing old emails and names in copyrightsgatecat2021-06-121-1/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Using hashlib in archesgatecat2021-06-021-32/+31
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Use hashlib for core netlist structuresgatecat2021-06-021-40/+40
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* nexus: Use new cluster APIgatecat2021-05-061-8/+12
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* nexus: Support for hard DPHYgatecat2021-03-081-1/+29
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Replace DelayInfo with DelayPair/DelayQuadgatecat2021-02-191-3/+6
| | | | | | | | | | | | | | | | | This replaces the arch-specific DelayInfo structure with new DelayPair (min/max only) and DelayQuad (min/max for both rise and fall) structures that form part of common code. This further reduces the amount of arch-specific code; and also provides useful data structures for timing analysis which will need to delay with pairs/quads of delays as it is improved. While there may be a small performance cost to arches that didn't separate the rise/fall cases (arches that aren't currently separating the min/max cases just need to be fixed...) in DelayInfo, my expectation is that inlining will mean this doesn't make much difference. Signed-off-by: gatecat <gatecat@ds0.me>
* Mark IdString and IdStringList single argument constructors explicit.Keith Rothman2021-02-041-1/+1
| | | | | | | | | Single argument constructors will silently convert to that type. This is typically not the right thing to do. For example, the nexus and ice40 arch_pybindings.h files were incorrectly parsing bel name strings, etc. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* nexus: Implement IdStringList for all arch object namesD. Shah2021-02-021-1/+1
| | | | Signed-off-by: D. Shah <dave@ds0.me>
* cleanup: Fix compiler warningsD. Shah2021-01-281-2/+1
| | | | Signed-off-by: D. Shah <dave@ds0.me>
* nexus: Add MULTADDSUB9X9WIDE supportDavid Shah2020-12-081-28/+55
| | | | Signed-off-by: David Shah <dave@ds0.me>
* nexus: Add support for initialised LRAMDavid Shah2020-12-071-2/+5
| | | | Signed-off-by: David Shah <dave@ds0.me>
* nexus: Add basic LRAM support (no init)David Shah2020-12-021-2/+55
| | | | Signed-off-by: David Shah <dave@ds0.me>
* nexus: Add PLL supportDavid Shah2020-12-021-2/+74
| | | | Signed-off-by: David Shah <dave@ds0.me>
* nexus: Add support for deriving timing constraints in packerDavid Shah2020-12-021-0/+96
| | | | Signed-off-by: David Shah <dave@ds0.me>
* nexus: Preliminary integration of DSP timing dataDavid Shah2020-11-301-4/+58
| | | | Signed-off-by: David Shah <dave@ds0.me>
* nexus: Clocked MULTADDSUB36X36 fixDavid Shah2020-11-301-0/+2
| | | | Signed-off-by: David Shah <dave@ds0.me>
* nexus: Add MULTADDSUB36X36David Shah2020-11-301-4/+21
| | | | Signed-off-by: David Shah <dave@ds0.me>
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