diff options
author | Maciej Kurc <mkurc@antmicro.com> | 2022-03-11 16:05:37 +0100 |
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committer | Maciej Kurc <mkurc@antmicro.com> | 2022-03-16 09:20:15 +0100 |
commit | 43861c0ee298c4d2a5cc89a42e816299c7f86138 (patch) | |
tree | 4555ccf228f5c3a486dcddd302b222dc1fed2f49 /nexus/pack.cc | |
parent | 74783c0c0951b84e22d6d9e1b578694e77d7cfb4 (diff) | |
download | nextpnr-43861c0ee298c4d2a5cc89a42e816299c7f86138.tar.gz nextpnr-43861c0ee298c4d2a5cc89a42e816299c7f86138.tar.bz2 nextpnr-43861c0ee298c4d2a5cc89a42e816299c7f86138.zip |
nexus: Added support for the DCS Bel
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
Diffstat (limited to 'nexus/pack.cc')
-rw-r--r-- | nexus/pack.cc | 25 |
1 files changed, 23 insertions, 2 deletions
diff --git a/nexus/pack.cc b/nexus/pack.cc index 66d897a8..cc86699a 100644 --- a/nexus/pack.cc +++ b/nexus/pack.cc @@ -860,6 +860,9 @@ struct NexusPacker // Skip undriven nets; and nets that are already global if (ni->driver.cell == nullptr) continue; + if (ni->driver.cell->type == id_DCS) { + continue; + } if (ni->driver.cell->type == id_DCC) { --available_globals; continue; @@ -1981,14 +1984,32 @@ struct NexusPacker if (user.port == id_CLKI || user.port == id_REFCK) changed_cells.insert(user.cell->name); auto &drv = ctx->nets.at(net)->driver; - if (iter == 1 && drv.cell != nullptr && (drv.port == id_HFCLKOUT || drv.port == id_LFCLKOUT)) - changed_cells.insert(drv.cell->name); + if (iter == 1 && drv.cell != nullptr) { + if (drv.cell->type == id_OSC_CORE && (drv.port == id_HFCLKOUT || drv.port == id_LFCLKOUT)) + changed_cells.insert(drv.cell->name); + if (drv.cell->type == id_DCC && drv.port == id_CLKO) + changed_cells.insert(drv.cell->name); + if (drv.cell->type == id_DCS && drv.port == id_DCSOUT) + changed_cells.insert(drv.cell->name); + } } changed_nets.clear(); for (auto cell : changed_cells) { CellInfo *ci = ctx->cells.at(cell).get(); if (ci->type == id_DCC) { copy_constraint(ci, id_CLKI, id_CLKO, 1); + } else if (ci->type == id_DCS) { + // For DCC copy the worst case ("fastest") constraint + delay_t period_clk0, period_clk1; + bool have_clk0 = get_period(ci, id_CLK0, period_clk0); + bool have_clk1 = get_period(ci, id_CLK1, period_clk1); + if (have_clk0 && !have_clk1) { + copy_constraint(ci, id_CLK0, id_DCSOUT); + } else if (!have_clk0 && have_clk1) { + copy_constraint(ci, id_CLK1, id_DCSOUT); + } else if ( have_clk0 && have_clk1) { + set_period(ci, id_DCSOUT, std::min(period_clk0, period_clk1)); + } } else if (ci->type == id_OSC_CORE) { int div = int_or_default(ci->params, id_HF_CLK_DIV, 128); const float tol = 1.07f; // OSCA has +/-7% frequency tolerance, assume the worst case. |