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* refactor: ArcBounds -> BoundingBoxgatecat2022-12-071-2/+2
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #1019 from antmicro/support-clock-relationsmyrtle2022-09-201-4/+11
|\ | | | | Support cross-domain clock relations in timing analyser
| * Code cleanupMaciej Kurc2022-08-311-4/+4
| | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
| * Fixed port timing classes of DCC ports in the Nexus architectureMaciej Kurc2022-08-301-4/+11
| | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
* | nexus: Add ES2 device names and --list-devicesgatecat2022-09-151-1/+35
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* refactor: Use IdString::in instead of || chainsgatecat2022-08-101-20/+17
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* nexus: Add timing data for LRAMgatecat2022-08-101-0/+16
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* refactor: id(stringf(...)) to new idf(...) helpergatecat2022-08-101-5/+5
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* clangformatgatecat2022-03-171-1/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* nexus: Added support for the DCS BelMaciej Kurc2022-03-161-0/+15
| | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
* nexus: Added FASM feature emission for DCC and port timing class infoMaciej Kurc2022-03-151-0/+8
| | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
* refactor: Use constids instead of id("..")gatecat2022-02-161-20/+20
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* nexus: Hotfix to disable unimplemented DCS routethrugatecat2022-02-031-1/+6
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* nexus: add option to modify the mult factor of the estimate delayAlessandro Comodi2022-02-011-1/+6
| | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* archapi: Use arbitrary rather than actual placement in predictDelaygatecat2021-12-191-7/+5
| | | | | | | | | | | | This makes predictDelay be based on an arbitrary belpin pair rather than a arc of a net based on cell placement. This way 'what-if' decisions can be evaluated without actually changing placement; potentially useful for parallel placement. A new helper predictArcDelay behaves like the old predictDelay to minimise the impact on existing passes; only arches need be updated. Signed-off-by: gatecat <gatecat@ds0.me>
* nexus: router1 speedup based on #867gatecat2021-12-171-0/+3
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* nexus: Add resource cost overridesgatecat2021-09-241-2/+19
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* nexus: LUT permutation supportgatecat2021-09-241-1/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #822 from YosysHQ/gatecat/nexus-split-vccgatecat2021-09-231-0/+3
|\ | | | | nexus: Support for split Vcc routing
| * nexus: Support for split Vcc routinggatecat2021-09-221-0/+3
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | Merge pull request #823 from YosysHQ/gatecat/nexus-r1-tweaksgatecat2021-09-221-1/+3
|\ \ | | | | | | nexus: Tweaks for router1 performance
| * | nexus: Tweaks for router1 performancegatecat2021-09-221-1/+3
| |/ | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* / nexus: Fix DSP macro placementgatecat2021-09-221-0/+42
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* nexus: Disable center DCC-thrus on 17k devicegatecat2021-06-161-0/+13
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Fixing old emails and names in copyrightsgatecat2021-06-121-1/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Use hashlib for core netlist structuresgatecat2021-06-021-4/+4
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* router2: Add heatmap by routing resource typegatecat2021-05-201-0/+11
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Revert "nexus: Enable placeAllAtOnce"gatecat2021-05-061-1/+4
| | | | This reverts commit 0abe425675ae0cc550194171f1f15ec4058a05d6.
* nexus: Enable placeAllAtOncegatecat2021-04-251-4/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* nexus: Fix copypastagatecat2021-03-081-1/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* nexus: Fail gracefully when seeing special pinsgatecat2021-03-051-1/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Replace DelayInfo with DelayPair/DelayQuadgatecat2021-02-191-14/+12
| | | | | | | | | | | | | | | | | This replaces the arch-specific DelayInfo structure with new DelayPair (min/max only) and DelayQuad (min/max for both rise and fall) structures that form part of common code. This further reduces the amount of arch-specific code; and also provides useful data structures for timing analysis which will need to delay with pairs/quads of delays as it is improved. While there may be a small performance cost to arches that didn't separate the rise/fall cases (arches that aren't currently separating the min/max cases just need to be fixed...) in DelayInfo, my expectation is that inlining will mean this doesn't make much difference. Signed-off-by: gatecat <gatecat@ds0.me>
* nexus: Switch to BaseArchD. Shah2021-02-051-14/+2
| | | | Signed-off-by: D. Shah <dave@ds0.me>
* Mark IdString and IdStringList single argument constructors explicit.Keith Rothman2021-02-041-3/+3
| | | | | | | | | Single argument constructors will silently convert to that type. This is typically not the right thing to do. For example, the nexus and ice40 arch_pybindings.h files were incorrectly parsing bel name strings, etc. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* nexus: Implement IdStringList for all arch object namesD. Shah2021-02-021-36/+34
| | | | Signed-off-by: D. Shah <dave@ds0.me>
* Run "make clangformat".Keith Rothman2021-02-021-2/+2
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Rename Partition -> BelBucket.Keith Rothman2021-02-021-3/+3
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Add Partition APIs to ice40, nexus, gowin archs.Keith Rothman2021-02-021-2/+15
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* nexus: Switch from RelPtr to RelSliceD. Shah2021-01-271-37/+31
| | | | | | | | | | This replaces RelPtrs and a separate length field with a Rust-style slice containing both a pointer and a length; with bounds checking always enforced. Thus iterating over these structures is both cleaner and safer. Signed-off-by: D. Shah <dave@ds0.me>
* nexus: Add basic LRAM support (no init)David Shah2020-12-021-0/+11
| | | | Signed-off-by: David Shah <dave@ds0.me>
* nexus: Fix db integrity checkDavid Shah2020-11-301-17/+6
| | | | Signed-off-by: David Shah <dave@ds0.me>
* nexus: Add post-place LUTFF optimisationDavid Shah2020-11-301-5/+23
| | | | Signed-off-by: David Shah <dave@ds0.me>
* nexus: Preliminary integration of DSP timing dataDavid Shah2020-11-301-0/+49
| | | | Signed-off-by: David Shah <dave@ds0.me>
* nexus: Tweak heuristics to improve routeabilityDavid Shah2020-11-301-2/+2
| | | | Signed-off-by: David Shah <dave@ds0.me>
* nexus: Fix slow routing around DSPsDavid Shah2020-11-301-0/+24
| | | | Signed-off-by: David Shah <dave@ds0.me>
* nexus: Tweak delay heuristicsDavid Shah2020-11-301-2/+4
| | | | Signed-off-by: David Shah <dave@ds0.me>
* nexus: Add EBR timing analysisDavid Shah2020-11-301-0/+19
| | | | Signed-off-by: David Shah <dave@ds0.me>
* nexus: Add LUTRAM and WIDEFN9 timing supportDavid Shah2020-11-301-3/+22
| | | | Signed-off-by: David Shah <dave@ds0.me>
* timing: Add a few more cell typesDavid Shah2020-11-301-6/+76
| | | | Signed-off-by: David Shah <dave@ds0.me>
* nexus: Swap sort order to make some lookups easierDavid Shah2020-11-301-2/+2
| | | | Signed-off-by: David Shah <dave@ds0.me>
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