| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | mistral: Add MISTRAL_CLKBUF cell type | gatecat | 2021-05-15 | 1 | -1/+1 |
| * | mistral: Fix ENA and ACLR bitstream generation | gatecat | 2021-05-15 | 1 | -2/+2 |
| * | mistral: Fix EF_SEL and BTO_DIS | gatecat | 2021-05-15 | 1 | -3/+3 |
| * | mistral: PKREG bits appear to be mirrored within a half? | gatecat | 2021-05-15 | 1 | -2/+3 |
| * | mistral: FF&CLKBUF fixes, part 1 | gatecat | 2021-05-15 | 1 | -1/+9 |
| * | mistral: First pass at FF and CLKBUF bitgen | gatecat | 2021-05-15 | 1 | -10/+102 |
| * | mistral: Carry fixes | gatecat | 2021-05-15 | 1 | -1/+2 |
| * | mistral: Carry debugging | gatecat | 2021-05-15 | 1 | -1/+4 |
| * | mistral: Write arith mode to bitstream (not yet functional) | gatecat | 2021-05-15 | 1 | -0/+3 |
| * | mistral: Write LUT inits | gatecat | 2021-05-15 | 1 | -0/+37 |
| * | mistral: Add some IO configuration | gatecat | 2021-05-15 | 1 | -0/+30 |
| * | mistral: Setting some more boilerplate bits | gatecat | 2021-05-15 | 1 | -0/+102 |
| * | mistral: Add stub RBF generation | gatecat | 2021-05-15 | 1 | -0/+84 |
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index : iCE40/nextpnr | |
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