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| * Merge masterMiodrag Milanovic2019-06-258-4/+83
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| * | enable lading of jsons and setting up contextMiodrag Milanovic2019-06-141-0/+2
| * | Use flags for each stepMiodrag Milanovic2019-06-142-3/+3
| * | restore arch info for ecp5Miodrag Milanovic2019-06-141-0/+3
| * | restore context from jsonMiodrag Milanovic2019-06-141-3/+43
| * | Load properties from json and propagate to context createMiodrag Milanovic2019-06-131-2/+2
| * | Save settings that we saved in projectMiodrag Milanovic2019-06-131-1/+1
| * | Remove concept of project and code connectedMiodrag Milanovic2019-06-131-76/+0
| * | Use properties for settings and save in jsonMiodrag Milanovic2019-06-121-1/+1
| * | Save top level attrs and store current stepMiodrag Milanovic2019-06-072-0/+3
| * | Add vcc and gnd nets and cells only if neededMiodrag Milanovic2019-06-071-5/+20
| * | CleanupMiodrag Milanovic2019-06-072-13/+0
| * | WIP saving/loading attributesMiodrag Milanovic2019-06-073-4/+23
| * | Revert "Do not add VCC if not used, loading json works"Miodrag Milanovic2019-06-021-6/+5
| * | Added support for attributes/properties typesMiodrag Milanovic2019-06-011-1/+1
| * | Do not add VCC if not used, loading json worksMiodrag Milanovic2019-05-311-5/+6
* | | Merge pull request #297 from whitequark/serialize-chipdbDavid Shah2019-06-271-21/+29
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| * | | CMake: serialize chipdb generation by default.whitequark2019-06-261-2/+10
| * | | CMake: formatting. NFC.whitequark2019-06-261-21/+21
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* | | Merge pull request #283 from tux3/warn_pcf_trailingDavid Shah2019-06-261-1/+4
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| * | ice40: Warn that trailing PCF settings are ignoredtux32019-05-311-1/+4
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* | clangformatDavid Shah2019-06-243-6/+12
* | ice40: add RGB_DRV/LED_DRV_CUR support for u4kSimon Schubert2019-06-108-4/+77
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* ice40: Add support for HFOSC trimmingSylvain Munaut2019-05-131-0/+5
* Merge pull request #270 from smunaut/sb_io_conflictDavid Shah2019-04-172-2/+38
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| * ice40: Check for SB_IO shared wires conflicts in isValidBelForCellSylvain Munaut2019-04-171-0/+36
| * ice40: In assignCellInfo get PIN_TYPE/NEG_TRIGGER from params and not attrsSylvain Munaut2019-04-171-2/+2
* | ice40: Only create padin gbuf for PLLs if global output actually usedSylvain Munaut2019-04-171-11/+38
* | ice40: Take placed SB_GBs into account when placing PLLsSylvain Munaut2019-04-161-9/+55
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* ice40/pack: During IO packing, remove any unused input connectionSylvain Munaut2019-04-111-0/+13
* ice40: Don't constrain to a PLL bel that has already been usedDavid Shah2019-04-011-0/+2
* ice40: Add support for SB_I2C and SB_SPISylvain Munaut2019-03-255-1/+112
* Add --placer option and refactor placer selectionDavid Shah2019-03-243-6/+16
* HeAP: Add PlacerHeapCfgDavid Shah2019-03-221-1/+3
* HeAP: Make HeAP placer optionalDavid Shah2019-03-222-5/+11
* HeAP: Add TAUCS wrapper and integrationDavid Shah2019-03-221-2/+4
* ice40: Add examples folder including floorplan exampleDavid Shah2019-03-2211-0/+42
* Add Python helper functions for floorplanningDavid Shah2019-03-221-0/+7
* ice40: Fix u4k in external chipdb mode.Marcin Kościelnicki2019-03-191-3/+3
* ice40: u4k merge fixDavid Shah2019-02-251-0/+2
* Merge pull request #239 from YosysHQ/dsp_casc_dummy_wiresDavid Shah2019-02-252-0/+24
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| * ice40: Add DSP SIGNEXTIN/OUT and ACCUMCI/O portsDavid Shah2019-02-212-0/+24
* | ice40: support u4kSimon Schubert2019-02-2313-13/+57
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* ice40: Fix timing class of 'padin' GB outputsDavid Shah2019-02-201-1/+1
* Merge branch 'master' into mmaped_chipdbMiodrag Milanović2019-02-121-1/+8
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| * ice40: PLLs can't conflict with themselvesDavid Shah2019-02-091-0/+2
| * ice40: Don't create PLLOUT_B buffer for single-output PLL variantsDavid Shah2019-02-091-1/+6
* | Fix according to comments on PRMiodrag Milanovic2019-02-101-1/+1
* | Load chipdb from filesystem as optionMiodrag Milanovic2019-02-093-83/+114
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* Merge pull request #220 from YosysHQ/coi3Eddie Hung2019-01-291-6/+9
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