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* streamline constant_net detectionrowanG0772023-02-061-2/+4
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* refactor: Use IdString::in instead of || chainsgatecat2022-08-101-4/+4
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* ice40: Fix propagation of constraints through SB_GBgatecat2022-05-081-7/+24
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* ice40: Merge driving LUT<=2s into carry-only LCsgatecat2022-03-291-0/+63
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* ice40: Improve error reporting for PLL conflictsgatecat2022-03-251-7/+32
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* clangformatgatecat2022-03-171-1/+2
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* ice40: fix crash when packing LUTs with no outputStefan Riesenberger2022-03-141-24/+27
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* Switch to potentially-sparse net users arraygatecat2022-02-271-44/+37
| | | | | | | | This uses a new data structure for net.users that allows gaps, so removing a port from a net is no longer an O(n) operation on the number of users the net has. Signed-off-by: gatecat <gatecat@ds0.me>
* refactor: New member functions to replace design_utilsgatecat2022-02-181-18/+18
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* refactor: Use constids instead of id("..")gatecat2022-02-161-187/+176
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* refactor: New NetInfo and CellInfo constructorsgatecat2022-02-161-14/+8
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* ice40: Pack LUT at start of carry chain if there is 1 candidategatecat2021-12-141-0/+2
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* ice40: Use default value when IP is missing BUS_ADDR74 parametergatecat2021-07-201-3/+4
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* ice40: Fix order of values in errorgatecat2021-07-101-1/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Fixing old emails and names in copyrightsgatecat2021-06-121-3/+3
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Using hashlib in archesgatecat2021-06-021-10/+9
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Use hashlib for core netlist structuresgatecat2021-06-021-31/+34
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Replace DelayInfo with DelayPair/DelayQuadgatecat2021-02-191-7/+7
| | | | | | | | | | | | | | | | | This replaces the arch-specific DelayInfo structure with new DelayPair (min/max only) and DelayQuad (min/max for both rise and fall) structures that form part of common code. This further reduces the amount of arch-specific code; and also provides useful data structures for timing analysis which will need to delay with pairs/quads of delays as it is improved. While there may be a small performance cost to arches that didn't separate the rise/fall cases (arches that aren't currently separating the min/max cases just need to be fixed...) in DelayInfo, my expectation is that inlining will mean this doesn't make much difference. Signed-off-by: gatecat <gatecat@ds0.me>
* ice40: Use snake case for arch-specific functionsD. Shah2021-02-031-6/+6
| | | | | | | This makes the difference clearer between the general arch API that everyone must implement; and helper functions specific to one arch. Signed-off-by: D. Shah <dave@ds0.me>
* ice40: Implement IdStringList for all arch object namesD. Shah2021-02-021-14/+14
| | | | Signed-off-by: D. Shah <dave@ds0.me>
* refactor: Replace getXName().c_str(ctx) with ctx->nameOfXD. Shah2021-02-021-5/+4
| | | | | | This makes the ongoing migration to IdStringList easier. Signed-off-by: D. Shah <dave@ds0.me>
* ice40: Switch from RelPtr to RelSliceD. Shah2021-01-271-8/+5
| | | | | | | | | | This replaces RelPtrs and a separate length field with a Rust-style slice containing both a pointer and a length; with bounds checking always enforced. Thus iterating over these structures is both cleaner and safer. Signed-off-by: D. Shah <dave@ds0.me>
* ice40: Nicer error for unconstrained SB_GB_IODavid Shah2020-12-271-0/+2
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ice40: Clarify feedback paths in PLL constraints codeDavid Shah2020-12-031-3/+3
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ice40: Derive PLL timing constraintsDavid Shah2020-12-031-31/+138
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ice40/pack/SB_PLL: Force fixed value to 4'b1111 if dynamic delay is usedSylvain Munaut2020-11-101-7/+9
| | | | | | | | It's been confirmed that : (1) this is required by the hardware (2) icecube will force that field to 4'b1111 in fixed mode Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* ice40: If IO is used by SB_GB_IO, can't use it for PLLSylvain Munaut2020-07-091-1/+2
| | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* ice40: Derive oscillator frequency constraintsDavid Shah2020-03-291-0/+40
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ice40: Always copy DFF attrs to LCDavid Shah2020-03-191-0/+5
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Preserve hierarchy through packingDavid Shah2019-12-271-0/+1
| | | | Signed-off-by: David Shah <dave@ds0.me>
* frontend/generic: Fix regressionsDavid Shah2019-12-271-1/+3
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ice40: Preserve top level IO properlyDavid Shah2019-10-191-13/+3
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ice40: Add support for PLL DELAY_ADJUSTMENT_MODEDavid Shah2019-09-231-1/+15
| | | | | | Fixes #336 Signed-off-by: David Shah <dave@ds0.me>
* ice40: Move clock constraints across SB_IO and SB_GB_IODavid Shah2019-09-131-0/+20
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ice40: Add better stats on LC packingDavid Shah2019-08-081-1/+11
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ice40: Fix regressionDavid Shah2019-08-051-1/+3
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Major Property improvements for common and iCE40David Shah2019-08-051-29/+31
| | | | Signed-off-by: David Shah <dave@ds0.me>
* clangformat runMiodrag Milanovic2019-06-251-17/+15
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* Merge masterMiodrag Milanovic2019-06-251-4/+33
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| * clangformatDavid Shah2019-06-241-3/+5
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * ice40: add RGB_DRV/LED_DRV_CUR support for u4kSimon Schubert2019-06-101-4/+31
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* | Use flags for each stepMiodrag Milanovic2019-06-141-1/+1
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* | Save top level attrs and store current stepMiodrag Milanovic2019-06-071-0/+1
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* | Add vcc and gnd nets and cells only if neededMiodrag Milanovic2019-06-071-5/+20
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* | WIP saving/loading attributesMiodrag Milanovic2019-06-071-0/+1
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* | Revert "Do not add VCC if not used, loading json works"Miodrag Milanovic2019-06-021-6/+5
| | | | | | | | This reverts commit f1b3a14bc23ccee6acaf6bbe27827523dc13c111.
* | Added support for attributes/properties typesMiodrag Milanovic2019-06-011-1/+1
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* | Do not add VCC if not used, loading json worksMiodrag Milanovic2019-05-311-5/+6
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* ice40: Add support for HFOSC trimmingSylvain Munaut2019-05-131-0/+5
| | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* ice40: Only create padin gbuf for PLLs if global output actually usedSylvain Munaut2019-04-171-11/+38
| | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
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