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author | gatecat <gatecat@ds0.me> | 2021-02-19 10:39:57 +0000 |
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committer | gatecat <gatecat@ds0.me> | 2021-02-19 11:31:33 +0000 |
commit | 7922b3bfc4ef93b8f67194c05e1a236b4c83c3da (patch) | |
tree | b2b21259e030edd0adc7cc944322e3e9186d3a71 /ice40/pack.cc | |
parent | 8376db94a7519406444988be3628a4dadfb8d742 (diff) | |
download | nextpnr-7922b3bfc4ef93b8f67194c05e1a236b4c83c3da.tar.gz nextpnr-7922b3bfc4ef93b8f67194c05e1a236b4c83c3da.tar.bz2 nextpnr-7922b3bfc4ef93b8f67194c05e1a236b4c83c3da.zip |
Replace DelayInfo with DelayPair/DelayQuad
This replaces the arch-specific DelayInfo structure with new DelayPair
(min/max only) and DelayQuad (min/max for both rise and fall) structures
that form part of common code.
This further reduces the amount of arch-specific code; and also provides
useful data structures for timing analysis which will need to delay
with pairs/quads of delays as it is improved.
While there may be a small performance cost to arches that didn't
separate the rise/fall cases (arches that aren't currently separating
the min/max cases just need to be fixed...) in DelayInfo, my expectation
is that inlining will mean this doesn't make much difference.
Signed-off-by: gatecat <gatecat@ds0.me>
Diffstat (limited to 'ice40/pack.cc')
-rw-r--r-- | ice40/pack.cc | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/ice40/pack.cc b/ice40/pack.cc index 18bc90aa..51138a22 100644 --- a/ice40/pack.cc +++ b/ice40/pack.cc @@ -1085,17 +1085,17 @@ void set_period(Context *ctx, CellInfo *ci, IdString port, delay_t period) if (to == nullptr) return; if (to->clkconstr != nullptr) { - if (!equals_epsilon(to->clkconstr->period.delay, period)) + if (!equals_epsilon(to->clkconstr->period.maxDelay(), period)) log_warning(" Overriding derived constraint of %.1f MHz on net %s with user-specified constraint of " "%.1f MHz.\n", - MHz(ctx, to->clkconstr->period.delay), to->name.c_str(ctx), MHz(ctx, period)); + MHz(ctx, to->clkconstr->period.maxDelay()), to->name.c_str(ctx), MHz(ctx, period)); return; } to->clkconstr = std::unique_ptr<ClockConstraint>(new ClockConstraint()); - to->clkconstr->low.delay = period / 2; - to->clkconstr->high.delay = period / 2; - to->clkconstr->period.delay = period; - log_info(" Derived frequency constraint of %.1f MHz for net %s\n", MHz(ctx, to->clkconstr->period.delay), + to->clkconstr->low = DelayPair(period / 2); + to->clkconstr->high = DelayPair(period / 2); + to->clkconstr->period = DelayPair(period); + log_info(" Derived frequency constraint of %.1f MHz for net %s\n", MHz(ctx, to->clkconstr->period.maxDelay()), to->name.c_str(ctx)); }; bool get_period(Context *ctx, CellInfo *ci, IdString port, delay_t &period) @@ -1105,7 +1105,7 @@ bool get_period(Context *ctx, CellInfo *ci, IdString port, delay_t &period) NetInfo *from = ci->ports.at(port).net; if (from == nullptr || from->clkconstr == nullptr) return false; - period = from->clkconstr->period.delay; + period = from->clkconstr->period.maxDelay(); return true; }; |