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path: root/ice40/chipdb.py
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* ice40: u4k merge fixDavid Shah2019-02-251-0/+2
* Merge pull request #239 from YosysHQ/dsp_casc_dummy_wiresDavid Shah2019-02-251-0/+19
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| * ice40: Add DSP SIGNEXTIN/OUT and ACCUMCI/O portsDavid Shah2019-02-211-0/+19
* | ice40: support u4kSimon Schubert2019-02-231-1/+1
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* ice40/chipdb: Add wires to global network for all cells that can drive itSylvain Munaut2018-11-191-4/+18
* ice40: Add GlobalNetowkrInfo in the chip databaseSylvain Munaut2018-11-191-36/+46
* ice40/chipdb: Fix LOCKED keyword support to include all packagesSylvain Munaut2018-11-191-1/+2
* Add more missing iCE40 gfx (LP/HX is complete now)Clifford Wolf2018-08-191-4/+0
* Add iCE40 gfx for span-4 wires between IO tilesClifford Wolf2018-08-191-2/+0
* Add iCE40 gfx for wires connecting fabric tiles and IO tilesClifford Wolf2018-08-181-0/+7
* Improve iCE40 gfx for IO tiles and RAM tilesClifford Wolf2018-08-181-21/+179
* Add ice40 wire attributes (grid position, segment list)Clifford Wolf2018-08-181-0/+7
* Get rid of old iCE40 id_ Arch membersClifford Wolf2018-08-081-0/+2
* Get rid of PortPin and BelType (ice40, generic, docs)Clifford Wolf2018-08-081-40/+34
* Add new iCE40 delay estimator and delay predictorClifford Wolf2018-08-041-1/+1
* Fix bug in ice40 chipdby.py add_wire() that moves some wires to X0/Y0Clifford Wolf2018-08-041-3/+7
* Merge branch 'master' of github.com:YosysHQ/nextpnr into lutpermClifford Wolf2018-08-041-1/+5
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| * ice40: Add SB_GB timing to databaseDavid Shah2018-08-041-1/+5
* | Proper ice40 wire typesClifford Wolf2018-08-031-42/+93
* | Add iCE40 pseudo-pips for lut permutationClifford Wolf2018-08-031-12/+35
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* Merge pull request #22 from YosysHQ/routethruClifford Wolf2018-08-031-3/+38
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| * Add LUT route-through pips to iCE40 architecture databaseClifford Wolf2018-08-021-3/+38
* | ice40: Use real cell timingsDavid Shah2018-08-021-5/+6
* | ice40: Adding cell timings to chipdbDavid Shah2018-08-021-0/+72
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* Use icestorm timing informationClifford Wolf2018-07-311-27/+42
* Add binary search to getBelPinWire() and getBelPinType()Clifford Wolf2018-07-311-8/+6
* Towards better ice40 timing dataClifford Wolf2018-07-301-7/+21
* cmake: Set --fast and --slow chipdb.py argumentsDavid Shah2018-07-301-1/+1
* Add ice40 chipdb.py --fast/--slowClifford Wolf2018-07-301-0/+30
* Add iCE40 fast/slow delay fields to chipdbClifford Wolf2018-07-301-3/+9
* Improvements in bbasmClifford Wolf2018-07-261-1/+2
* Use bbasm to create iCE40 chipdbClifford Wolf2018-07-241-273/+38
* Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnr into q3k/pllSergiusz Bazanski2018-07-241-37/+1
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| * Remove uphill/downhill bel pins from ice40 dbClifford Wolf2018-07-241-30/+0
| * ice40: Fix SPRAM and other primitives in corners other than (0, 0)David Shah2018-07-241-1/+1
* | ice40: move PLL->IO from pseudo pip to second uphill belSergiusz Bazanski2018-07-241-35/+3
* | ice40: emit list of upbels in chipdbSergiusz Bazanski2018-07-241-12/+18
* | ice40: Emit feed-through LUTs for PLL/LOCKSergiusz Bazanski2018-07-241-1/+1
* | ice40: Implement emitting PLLsSergiusz Bazanski2018-07-241-0/+41
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* Add Context::archcheck() and "nextpnr-ice40 --test"Clifford Wolf2018-07-231-40/+54
* Bugfix in iCE40 chipdb.pyClifford Wolf2018-07-231-3/+0
* Add Arch::getBelPinType() and Arch::getWireBelPins() in iCE40 archClifford Wolf2018-07-221-2/+27
* ice40: Add virtual padin wires for intoscs and GB_IOsDavid Shah2018-07-191-1/+14
* ice40: Adding data for extra cell configurationDavid Shah2018-07-191-3/+22
* Remove pip names from ice40 chip db to safe memoryClifford Wolf2018-07-151-1/+1
* Add iCE40 Pip gfxClifford Wolf2018-07-151-6/+24
* Fix ice40 gfx wire indicesClifford Wolf2018-07-131-1/+1
* Updates from clang-formatClifford Wolf2018-07-121-1/+3
* Fix ice40 wire segments in lutff complexClifford Wolf2018-07-121-2/+2
* Improve iCE40 wire database and gfxClifford Wolf2018-07-121-1/+34
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