| Commit message (Expand) | Author | Age | Files | Lines | ||
|---|---|---|---|---|---|---|
| ... | ||||||
| * | Set the default log to stdout | ZipCPU | 2018-06-07 | 1 | -1/+12 | |
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| | * | Initial (random) placer capability | ZipCPU | 2018-06-07 | 1 | -1/+12 | |
| * | | ice40: Refactor PortPin and add Python binding | David Shah | 2018-06-07 | 1 | -107/+4 | |
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| * | clang-format for design and chip codebase | Clifford Wolf | 2018-06-07 | 1 | -439/+440 | |
| * | Add ice40 geometry information | Clifford Wolf | 2018-06-06 | 1 | -1/+6 | |
| * | Add ice40 --test mode | Clifford Wolf | 2018-06-06 | 1 | -0/+9 | |
| * | Refactor Chip API and iCE40 database | Clifford Wolf | 2018-06-06 | 1 | -119/+231 | |
| * | Add iCE40 blockram bels | Clifford Wolf | 2018-06-04 | 1 | -0/+84 | |
| * | Replace GuiLine with GraphicElement | Clifford Wolf | 2018-06-04 | 1 | -7/+4 | |
| * | Add iCE40 SB_IO bels | Clifford Wolf | 2018-06-03 | 1 | -2/+15 | |
| * | Add ice40 ICESTORM_LC bels | Clifford Wolf | 2018-06-02 | 1 | -3/+22 | |
| * | Use singular in type names (BelRange, WireIterator) | Clifford Wolf | 2018-06-02 | 1 | -18/+18 | |
| * | Add DelayInfo struct | Clifford Wolf | 2018-05-29 | 1 | -2/+10 | |
| * | Progress in chip.h API | Clifford Wolf | 2018-05-26 | 1 | -28/+110 | |
| * | Progress in ice40 chipdb | Clifford Wolf | 2018-05-26 | 1 | -48/+115 | |
| * | Start work on iCE40 chipdb | Clifford Wolf | 2018-05-26 | 1 | -0/+224 | |
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index : iCE40/nextpnr | |
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