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ice40
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bitstream.cc
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Author
Age
Files
Lines
*
ice40/bitstream: Convert to UNIX line endings
Sylvain Munaut
2018-11-16
1
-1043
/
+1043
*
ice40: Remove unnecessary RAM assertion
David Shah
2018-11-16
1
-1
/
+0
*
ice40: Don't set colbuf bits for 384
David Shah
2018-11-11
1
-0
/
+2
*
clangformat
David Shah
2018-09-30
1
-4
/
+1
*
ice40: LVDS input bitstream support
David Shah
2018-09-24
1
-4
/
+48
*
do not break if there are no nets loaded from sym section
Miodrag Milanovic
2018-08-18
1
-4
/
+6
*
Get rid of PortPin and BelType (ice40, generic, docs)
Clifford Wolf
2018-08-08
1
-17
/
+17
*
API change: Use CellInfo* and NetInfo* as cell/net handles (common, ice40)
Clifford Wolf
2018-08-05
1
-24
/
+24
*
clangformat
Clifford Wolf
2018-08-05
1
-21
/
+22
*
ice40: Bitstream gen for LUT permutation
David Shah
2018-08-04
1
-8
/
+78
*
ice40: Add bitstream gen for routethru LUTs
David Shah
2018-08-03
1
-9
/
+58
*
ice40: Add HFOSC support, force fabric routing on oscillators for now
David Shah
2018-08-01
1
-0
/
+4
*
clangformat
Sergiusz Bazanski
2018-08-01
1
-2
/
+3
*
clangformat
Eddie Hung
2018-07-25
1
-3
/
+2
*
ice40: fixes before review
Sergiusz Bazanski
2018-07-24
1
-6
/
+6
*
ice40: move PLL->IO from pseudo pip to second uphill bel
Sergiusz Bazanski
2018-07-24
1
-15
/
+16
*
ice40: emit list of upbels in chipdb
Sergiusz Bazanski
2018-07-24
1
-1
/
+1
*
clang-format
Sergiusz Bazanski
2018-07-24
1
-14
/
+21
*
ice40: A slightly nicer way to do this.
Sergiusz Bazanski
2018-07-24
1
-46
/
+31
*
ice40: Refactor PLL/LOCK LUT splicing out into Arch::
Sergiusz Bazanski
2018-07-24
1
-0
/
+1
*
ice40: Implement emitting PLLs
Sergiusz Bazanski
2018-07-24
1
-14
/
+104
*
clangformat
David Shah
2018-07-23
1
-2
/
+3
*
Move to new API and remove deprecated
Miodrag Milanovic
2018-07-22
1
-36
/
+38
*
Rename getWireBelPin to getBelPinWire
Clifford Wolf
2018-07-22
1
-3
/
+3
*
Added driver and users for nets
Miodrag Milanovic
2018-07-21
1
-0
/
+8
*
Map ports to nets
Miodrag Milanovic
2018-07-21
1
-0
/
+14
*
create io cells out of asc
Miodrag Milanovic
2018-07-21
1
-0
/
+27
*
add cells that are in default state or no configuration
Miodrag Milanovic
2018-07-21
1
-0
/
+40
*
Add used cells and attach them to bels
Miodrag Milanovic
2018-07-21
1
-0
/
+39
*
Assign proper pips
Miodrag Milanovic
2018-07-21
1
-9
/
+27
*
add only missing net
Miodrag Milanovic
2018-07-21
1
-3
/
+6
*
fix introduced bug
Miodrag Milanovic
2018-07-21
1
-0
/
+2
*
Bind wires to net
Miodrag Milanovic
2018-07-20
1
-629
/
+637
*
Few more checks on parameters and error eol
Miodrag Milanovic
2018-07-20
1
-4
/
+4
*
Start adding bitstream reading for ice40
Miodrag Milanovic
2018-07-20
1
-33
/
+133
*
ice40: Packer and bitstream gen support for MAC16s
David Shah
2018-07-19
1
-1
/
+89
*
Reducing performance cost of asserts
David Shah
2018-07-19
1
-1
/
+1
*
ice40: Fixes for inverted clocks
David Shah
2018-07-18
1
-1
/
+1
*
ice40: Assign ArchArgs after packing
David Shah
2018-07-18
1
-2
/
+3
*
Revert "Make ice40::Arch thread-safe"
Sergiusz Bazanski
2018-07-14
1
-5
/
+5
*
Revert "Remove legacy access to state via Arch"
Sergiusz Bazanski
2018-07-14
1
-7
/
+6
*
Remove legacy access to state via Arch
Sergiusz Bazanski
2018-07-14
1
-6
/
+7
*
Make ice40::Arch thread-safe
Sergiusz Bazanski
2018-07-13
1
-5
/
+5
*
Updates from clang-format
Clifford Wolf
2018-07-12
1
-3
/
+2
*
Add NPNR_ASSERT_FALSE, use in bitstream.cc
David Shah
2018-07-04
1
-2
/
+2
*
refactor: Replace assert with NPNR_ASSERT
David Shah
2018-07-04
1
-11
/
+11
*
Fixed macros and includes for MSVC
Miodrag Milanovic
2018-07-03
1
-0
/
+1
*
ice40: UltraPlus SPRAM working
David Shah
2018-06-29
1
-0
/
+23
*
ice40: PLace legaliser produces a design that is at least routable for picosoc
David Shah
2018-06-28
1
-1
/
+2
*
CarryInSet added to bitstream gen, add counter tb
David Shah
2018-06-26
1
-0
/
+7
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