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* refactor: Use IdString::in instead of || chainsgatecat2022-08-101-1/+1
* ice40: Fix accidental creation of empty portsgatecat2022-06-251-9/+9
* refactor: Use constids instead of id("..")gatecat2022-02-161-1/+1
* Fixing old emails and names in copyrightsgatecat2021-06-121-3/+3
* Remove isValidBelForCellgatecat2021-02-161-115/+94
* ice40: Use snake case for arch-specific functionsD. Shah2021-02-031-5/+5
* ice40: Implement IdStringList for all arch object namesD. Shah2021-02-021-1/+1
* ice40: Check for SB_IO shared wires conflicts in isValidBelForCellSylvain Munaut2019-04-171-0/+36
* ice40: Add helper to know which global network is driven by a SB_GB BelSylvain Munaut2018-11-261-2/+1
* ice40: Introduce the concept of forPadIn SB_GBSylvain Munaut2018-11-191-0/+2
* ice40: Fix BEL validity check for PLL vs SB_IOSylvain Munaut2018-11-191-21/+20
* clangformatDavid Shah2018-09-301-2/+2
* ice40: Validity check for LVDS IODavid Shah2018-09-241-0/+21
* ice40: Remove obsolete belType memberDavid Shah2018-09-241-1/+1
* Rework Arch::logicCellsCompatible() to take pointer + size, allowing use of s...Eddie Hung2018-08-101-15/+16
* Make containers staticEddie Hung2018-08-091-5/+7
* Get rid of old iCE40 id_ Arch membersClifford Wolf2018-08-081-5/+5
* Get rid of PortPin and BelType (ice40, generic, docs)Clifford Wolf2018-08-081-8/+8
* API change: Use CellInfo* and NetInfo* as cell/net handles (common, ice40)Clifford Wolf2018-08-051-12/+10
* ice40: after reviewSergiusz Bazanski2018-07-251-2/+2
* ice40: support PLL40_*_PAD, fix pass-through LUT for LOCKSergiusz Bazanski2018-07-251-0/+4
* Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnr into q3k/pllSergiusz Bazanski2018-07-241-3/+4
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| * ice40: Remove use of deprecated APIsDavid Shah2018-07-241-3/+4
* | ice40: fixes before reviewSergiusz Bazanski2018-07-241-0/+1
* | ice40: move PLL->IO from pseudo pip to second uphill belSergiusz Bazanski2018-07-241-19/+21
* | ice40: emit list of upbels in chipdbSergiusz Bazanski2018-07-241-1/+1
* | ice40: Prevent placement of SB_IOs in IO blocks used by PLL outputsSergiusz Bazanski2018-07-241-0/+24
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* Rename getWireBelPin to getBelPinWireClifford Wolf2018-07-221-1/+1
* ice40: Optimise reset/enable net checkingDavid Shah2018-07-201-10/+4
* ice40: Use xArchArgs in validity checkDavid Shah2018-07-181-22/+14
* Revert "Make PnR use Unlocked methods"Sergiusz Bazanski2018-07-141-3/+3
* Revert "Introduce proxies for locked access to ctx"Sergiusz Bazanski2018-07-141-38/+37
* Revert "Refactor proxies to nextpnr."Sergiusz Bazanski2018-07-141-3/+3
* Refactor proxies to nextpnr.Sergiusz Bazanski2018-07-141-3/+3
* Introduce proxies for locked access to ctxSergiusz Bazanski2018-07-131-37/+38
* Make PnR use Unlocked methodsSergiusz Bazanski2018-07-131-3/+3
* refactor: Replace assert with NPNR_ASSERTDavid Shah2018-07-041-2/+2
* ice40: Reworking placement legalisation to allow integration with SA placerDavid Shah2018-06-291-9/+0
* nets and cells are unique_ptr'sMiodrag Milanovic2018-06-251-3/+3
* Refactor: remove PlacementValidityChecker and move methods to ArchDavid Shah2018-06-251-39/+32
* Update from increased clangformat line lengthDavid Shah2018-06-231-17/+9
* Refactoring bind/unbind APIClifford Wolf2018-06-231-3/+3
* ice40: Move global net test to ArchDavid Shah2018-06-231-4/+5
* Cleanup almost all deprecation warningsMiodrag Milanovic2018-06-231-3/+3
* Switched from clifford@clifford.at to clifford@symbioticeda.com for copyright...Clifford Wolf2018-06-221-1/+1
* Major performance improvement to placement validity checkDavid Shah2018-06-191-21/+30
* ice40: Don't deduplicate local tracks when countingDavid Shah2018-06-191-10/+9
* Getting rid of old IdString API users, Add ctx to many internal APIsClifford Wolf2018-06-181-8/+9
* Rename Design to Context, derive from Arch instead of instantiatingClifford Wolf2018-06-181-17/+15
* Rename Chip to Arch and ChipArgs to ArchArgsClifford Wolf2018-06-181-2/+2
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