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* ice40: Validity check for LVDS IODavid Shah2018-09-241-0/+2
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* ice40: Remove obsolete belType memberDavid Shah2018-09-241-1/+0
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* Add more missing iCE40 gfx (LP/HX is complete now)Clifford Wolf2018-08-191-0/+46
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add iCE40 gfx for IO span-4 cornersClifford Wolf2018-08-191-1/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add iCE40 gfx for span-4 wires between IO tilesClifford Wolf2018-08-191-3/+9
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #47 from YosysHQ/settings_propagateClifford Wolf2018-08-181-11/+2
|\ | | | | Use settings for placer1 and router1
| * Use settings for placer1 and router1Miodrag Milanovic2018-08-091-11/+2
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* | Improve iCE40 gfx for IO tiles and RAM tilesClifford Wolf2018-08-181-2/+6
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Add ice40 wire attributes (grid position, segment list)Clifford Wolf2018-08-181-0/+33
|/ | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge branch 'master' of github.com:YosysHQ/nextpnr into constidsClifford Wolf2018-08-081-22/+77
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| * ice40: Add error for unknown cell type when getting timing infoDavid Shah2018-08-081-1/+3
| | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
| * Arch API: Removing Arch::isIOCellDavid Shah2018-08-081-2/+0
| | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
| * ice40: Add timing arcs through global buffersDavid Shah2018-08-081-0/+4
| | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
| * timing: Debugging implementation of new timing APIDavid Shah2018-08-081-1/+1
| | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
| * ice40: Timing arch fixDavid Shah2018-08-081-3/+17
| | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
| * timing: Update to new use API (currently broken)David Shah2018-08-081-2/+2
| | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
| * Arch API: New specification for timing port classesDavid Shah2018-08-081-18/+50
| | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
| * clangformatEddie Hung2018-08-061-10/+12
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| * Merge branch 'master' into assign_budget_speedupEddie Hung2018-08-061-2/+17
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| * | Add new Arch::isIOCell() API functionEddie Hung2018-08-061-0/+5
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* | | Get rid of old iCE40 id_ Arch membersClifford Wolf2018-08-081-43/+20
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | Get rid of PortPin and BelType (ice40, generic, docs)Clifford Wolf2018-08-081-110/+20
| |/ |/| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | ice40's getBudgetOverride() to return correct delay for different devicesEddie Hung2018-08-061-2/+17
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* Fix ice40's getBudgetOverride() to override only for COUT -> CINEddie Hung2018-08-061-1/+1
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* Change getBudgetOverride() signature to return bool and modify budget in placeEddie Hung2018-08-061-4/+6
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* API change: Use CellInfo* and NetInfo* as cell/net handles (common, ice40)Clifford Wolf2018-08-051-3/+3
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* clangformatClifford Wolf2018-08-051-34/+32
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* Add new iCE40 delay estimator and delay predictorClifford Wolf2018-08-041-58/+0
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add generation of models to tmfuzzClifford Wolf2018-08-041-0/+30
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Refactor ice40 timing fuzzer used to create delay estimatesClifford Wolf2018-08-041-16/+0
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge branch 'master' of github.com:YosysHQ/nextpnr into lutpermClifford Wolf2018-08-041-1/+6
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| * clangformatDavid Shah2018-08-041-1/+2
| | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
| * Add constraint weight as a command line optionDavid Shah2018-08-031-1/+5
| | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
* | Proper ice40 wire typesClifford Wolf2018-08-031-0/+39
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Add iCE40 pseudo-pips for lut permutationClifford Wolf2018-08-031-2/+15
|/ | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* ice40: Use real cell timingsDavid Shah2018-08-021-22/+17
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* Add Router1CfgClifford Wolf2018-08-021-1/+5
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Remove getFrameDecal() APIClifford Wolf2018-08-011-12/+0
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* clangformat for stuff I've touchedEddie Hung2018-07-311-12/+14
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* Modify the getNetinfo*() functions and getBudgetOverride() to not useEddie Hung2018-07-311-2/+1
| | | | user_idx and to take a PortRef& instead
* Merge remote-tracking branch 'origin/estdelay' into redist_slackEddie Hung2018-07-311-16/+20
|\ | | | | | | | | | | | | Conflicts: ecp5/arch.cc generic/arch.cc ice40/arch.cc
| * Modify predictDelay signatureEddie Hung2018-07-301-8/+13
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| * Add predictDelay Arch APIClifford Wolf2018-07-301-0/+16
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Merge branch 'redist_slack' into 'redist_slack'Eddie Hung2018-07-311-0/+31
|\ \ | | | | | | | | | # Conflicts: # common/timing.cc
| * | clangformatEddie Hung2018-07-281-5/+6
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| * | ice40 estimateDelay to account for out/in muxesEddie Hung2018-07-271-0/+16
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| * | getBudgetOverride() now handles COUT crossing tilesEddie Hung2018-07-261-5/+12
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| * | Revert "Remove Arch::getBudgetOverride()"Eddie Hung2018-07-261-0/+7
| |/ | | | | | | This reverts commit 749dae4ae5b2b719237af5db28e98ff671bae265.
* | getChipName() should be constClifford Wolf2018-07-311-1/+1
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Add binary search to getBelPinWire() and getBelPinType()Clifford Wolf2018-07-311-7/+36
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
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