aboutsummaryrefslogtreecommitdiffstats
path: root/gowin/arch.cc
Commit message (Expand)AuthorAgeFilesLines
* gowin: fix styleYRabbit2023-04-201-16/+16
* gowin: fix styleYRabbit2023-04-201-1/+1
* gowin: add a common mechanism for placing portsYRabbit2023-04-201-53/+33
* gowin: Remove inherited code for ODDR(c)YRabbit2023-04-141-70/+9
* gowin: Fix styleYRabbit2023-04-121-1/+1
* gowin: implement IDES16 and OSER16 primitivesYRabbit2023-04-121-5/+157
* gowin: Add implementation of IDDR and IDDRC primitivesYRabbit2023-04-061-3/+3
* gowin: Add support for IDES primitivesYRabbit2023-04-041-15/+12
* gowin: bugfixYRabbit2023-03-231-1/+1
* gowin: Rename questionable portsYRabbit2023-03-231-20/+20
* gowin: Add support for OSER primitivesYRabbit2023-03-231-20/+139
* cmake: Make HeAP placer always-enabledgatecat2023-03-171-9/+1
* gowin: Add bels for new types of oscillatoruis2023-02-061-0/+19
* gowin: Add PLL support for the GW1NS-2C chipYRabbit2023-01-311-0/+7
* gowin: Add PLL support for GW1NR-4 chipsYRabbit2023-01-311-1/+5
* gowin: Proper use of the C++ mechanismsYRabbit2023-01-301-1/+1
* gowin: Add PLL support for the GW1NR-9 chipYRabbit2023-01-301-45/+45
* gowin: Add PLL support for the GW1NR-9C chipYRabbit2023-01-261-35/+63
* gowin: to use the FB network detection functionYRabbit2023-01-191-0/+6
* gowin: add a PLL primitive for the GW1NS-4 seriesYRabbit2023-01-181-10/+108
* gowin: improve clock wire routingYRabbit2022-12-301-0/+10
* gowin: correct the delay calculationYRabbit2022-12-291-5/+16
* gowin: fix build for wasmYRabbit2022-12-211-0/+8
* gowin: BUGFIX: Correctly handle resetsYRabbit2022-12-091-13/+0
* Merge pull request #1059 from YosysHQ/gatecat/validity-errorsmyrtle2022-12-071-1/+1
|\
| * api: add explain_invalid option to isBelLocationValidgatecat2022-12-071-1/+1
* | Merge pull request #1058 from YosysHQ/gatecat/bounds-refactormyrtle2022-12-071-2/+2
|\|
| * refactor: ArcBounds -> BoundingBoxgatecat2022-12-071-2/+2
* | gowin: change the way networks are handledYRabbit2022-12-061-7/+8
* | gowin: add PLL pins processingYRabbit2022-12-041-4/+119
|/
* gowin: add information about pin configurationsYRabbit2022-11-251-2/+13
* gowin: use ctx->idf() a bitYRabbit2022-11-111-7/+3
* gowin: add initial PLL supportYRabbit2022-11-101-0/+40
* run clangformatgatecat2022-10-171-1/+2
* support windows line endingsLushay Labs2022-10-091-4/+4
* gowin: BUGFIX. Really memorize the chipYRabbit2022-08-251-0/+2
* gowin: Remove incomprehensible names of the muxesYRabbit2022-07-191-6/+9
* gowin: Remove unnecessary functionsYRabbit2022-07-051-28/+8
* Merge branch 'master' into clock-wipYRabbit2022-07-051-0/+30
|\
| * Merge branch 'master' into shadowramPepijn de Vos2022-07-021-11/+213
| |\
| * | hook up CE maybePepijn de Vos2022-06-161-0/+2
| * | lutram actually PnRsPepijn de Vos2022-06-061-36/+28
| * | WIP shadowramPepijn de Vos2022-06-051-0/+36
* | | gowin: fix compilationYRabbit2022-07-041-0/+1
* | | gowin: Let the placer know about global networksYRabbit2022-07-041-1/+55
* | | gowin: add a separate router for the clocksYRabbit2022-06-231-0/+15
| |/ |/|
* | gowin: Use local aliasesYRabbit2022-06-091-7/+11
* | gowin: Add support for long wiresYRabbit2022-05-271-4/+202
|/
* gowin: Add initial syntax support for long wiresYRabbit2022-05-021-7/+27
* gowin: handle the GW1N-9 feature.YRabbit2022-04-031-2/+17
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-29 03:21:12 +0000