iCE40/nextpnr - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Change how package pin IO sites are selected.	Keith Rothman	2021-02-17	3	-16/+52
*	Change makefiles to build a FPGA interchange BBA.	Keith Rothman	2021-02-17	4	-16/+106
*	Add examples invoking FPGA interchange nextpnr.	Keith Rothman	2021-02-17	11	-0/+152
*	Continue fixes.	Keith Rothman	2021-02-17	5	-23/+93
*	Disable traversal limit when reading logical netlist.	Keith Rothman	2021-02-17	1	-1/+3
*	Add initial site router.	Keith Rothman	2021-02-17	4	-6/+813
*	Working on standing up initial constraints system.	Keith Rothman	2021-02-17	3	-25/+468
*	clangformat	gatecat	2021-02-17	1	-3/+4
*	Merge pull request #586 from litghost/add_cell_bel_mapping_only	gatecat	2021-02-17	2	-13/+274
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\| *	Require `--package` when arch BBA contains multiple packages.	Keith Rothman	2021-02-16	1	-3/+11
\| *	[FPGA Interchange] Add Cell -> BEL Pin maps.	Keith Rothman	2021-02-16	2	-13/+266
* \|	Remove isValidBelForCell	gatecat	2021-02-16	2	-14/+0
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*	Move CMake logic into fpga-interchange-schema.	Keith Rothman	2021-02-15	1	-13/+1
*	Small fixes from review.	Keith Rothman	2021-02-15	1	-1/+1
*	Add FPGA interchange frontend and backend.	Keith Rothman	2021-02-15	6	-4/+914
*	Merge pull request #575 from YosysHQ/gatecat/belpin-2	gatecat	2021-02-15	1	-0/+3
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\| *	Add getBelPinsForCellPin to Arch API	gatecat	2021-02-10	1	-0/+3
* \|	Run "make clangformat".	Keith Rothman	2021-02-12	4	-66/+53
* \|	Remove capnp and libz for XDC parser PR.	Keith Rothman	2021-02-12	1	-4/+0
* \|	Refactor XDC parser into a little class for testing purposes.	Keith Rothman	2021-02-12	3	-14/+52
* \|	Add unknown handles to convert [0] to "[0]".	Keith Rothman	2021-02-12	1	-0/+11
* \|	Add FPGA interchange XDC parser.	Keith Rothman	2021-02-12	5	-3/+204
* \|	Add getBelHidden and add some missing "override" statements.	Keith Rothman	2021-02-11	1	-2/+1
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*	interchange: Base on ArchAPI	D. Shah	2021-02-08	2	-106/+135
*	Add RelSlice::ssize and use it when comparing with signed ints.	Keith Rothman	2021-02-05	2	-27/+28
*	Move all string data into BBA file.	Keith Rothman	2021-02-05	4	-48901/+15
*	Use RelSlice instead of RelPtr in cases where sizes are present.	Keith Rothman	2021-02-04	2	-97/+67
*	Update APIs to conform to style guide.	Keith Rothman	2021-02-04	5	-67/+48939
*	Remove unused method getReservedWireNet.	Keith Rothman	2021-02-04	1	-7/+0
*	Update copywrite headers.	Keith Rothman	2021-02-04	6	-4/+10
*	Correct some typos.	Keith Rothman	2021-02-04	1	-4/+4
*	Fix warnings with signed/unsigned.	Keith Rothman	2021-02-04	1	-1/+1
*	Fix fpga_interchange/README.md duplicate patch statement.	Keith Rothman	2021-02-04	1	-8/+0
*	Fix URLs in Markdown.	Keith Rothman	2021-02-04	1	-2/+2
*	Add empty constids.inc for build.	Keith Rothman	2021-02-04	1	-0/+0
*	Run "make clangformat".	Keith Rothman	2021-02-04	4	-148/+100
*	Add README about initial state of FPGA interchange implementation.	Keith Rothman	2021-02-04	1	-0/+170
*	Update FPGA interchange to use IdStringList.	Keith Rothman	2021-02-04	2	-132/+137
*	Start adding data for placement constraint solving.	Keith Rothman	2021-02-04	2	-50/+43
*	Debug BEL bucket data.	Keith Rothman	2021-02-04	1	-11/+14
*	Add initial updates to FPGA interchange arch for BEL buckets.	Keith Rothman	2021-02-04	5	-0/+247
*	Address review comments.	Keith Rothman	2021-02-04	3	-95/+6
*	Fix BBA import bugs.	Keith Rothman	2021-02-04	2	-69/+201
*	Assorted fixes to new FPGA interchange based arch.	Keith Rothman	2021-02-04	3	-5/+13
*	Initial compiling version.	Keith Rothman	2021-02-04	2	-16/+25
*	Initial FPGA interchange (which is just a cut-down xilinx arch).	Keith Rothman	2021-02-04	9	-0/+2102