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* clangformatgatecat2021-03-033-114/+108
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Update FPGA interchange README.Keith Rothman2021-02-261-11/+7
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* For now just return false in the site router.Keith Rothman2021-02-261-1/+1
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Initial LUT rotation logic.Keith Rothman2021-02-267-7/+739
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Add counter test.Keith Rothman2021-02-265-0/+71
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Fix compiler warnings introduced by -Wextragatecat2021-02-252-3/+3
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Fix assorted bugs in FPGA interchange.Keith Rothman2021-02-238-422/+626
| | | | | | | | | | Fixes: - Only use map constant pins during routing, and not during placement. - Unmapped cell ports have no BEL pins. - Fix SiteRouter congestion not taking into account initial expansion. - Fix psuedo-site pip output. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Finish dedicated interconnect implementation.Keith Rothman2021-02-233-139/+611
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Working FF example now that constant merging is done.Keith Rothman2021-02-236-8/+218
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Add initial logic for handling dedicated interconnect situations.Keith Rothman2021-02-2311-26/+587
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Move RapidWright git URI back to upstream.Keith Rothman2021-02-231-5/+1
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Remove some signedness warnings.Keith Rothman2021-02-231-1/+1
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Fix reference copy.Keith Rothman2021-02-231-6/+6
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Run "make clangformat".Keith Rothman2021-02-231-6/+8
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Initial working constant network support!Keith Rothman2021-02-234-14/+145
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Add constant network test case.Keith Rothman2021-02-235-0/+42
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Add tests to confirm constant routing import.Keith Rothman2021-02-232-0/+36
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Correct some bugs in the create_bba Makefile.Keith Rothman2021-02-231-3/+9
| | | | | | Also add debug_test target to debug archcheck. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Add initial constant network support to FPGA interchange arch.Keith Rothman2021-02-232-7/+47
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Change CellInfo in getBelPinsForCellPin to be const.Keith Rothman2021-02-231-1/+1
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Replace DelayInfo with DelayPair/DelayQuadgatecat2021-02-193-36/+5
| | | | | | | | | | | | | | | | | This replaces the arch-specific DelayInfo structure with new DelayPair (min/max only) and DelayQuad (min/max for both rise and fall) structures that form part of common code. This further reduces the amount of arch-specific code; and also provides useful data structures for timing analysis which will need to delay with pairs/quads of delays as it is improved. While there may be a small performance cost to arches that didn't separate the rise/fall cases (arches that aren't currently separating the min/max cases just need to be fixed...) in DelayInfo, my expectation is that inlining will mean this doesn't make much difference. Signed-off-by: gatecat <gatecat@ds0.me>
* Fix sign mismatch.Keith Rothman2021-02-182-2/+2
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Do some spell checking on site_router.ccKeith Rothman2021-02-181-18/+18
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Add some utility methods for site instance access.Keith Rothman2021-02-183-13/+42
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Update README's with latest instructions and features.Keith Rothman2021-02-183-20/+94
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Add utility targets for getting plain text outputs.Keith Rothman2021-02-171-1/+5
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Add IOSTANDARD to ports.Keith Rothman2021-02-171-1/+3
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Emit fixed attributes to output physical netlist.Keith Rothman2021-02-171-8/+19
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Refactor "get only from iterator" to a utility.Keith Rothman2021-02-173-12/+9
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Keep all build artifacts under create_bba/build.Keith Rothman2021-02-172-4/+5
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Change how package pin IO sites are selected.Keith Rothman2021-02-173-16/+52
| | | | | | | The first site type that matches is now selected, under the premise that the early site types are more general. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Change makefiles to build a FPGA interchange BBA.Keith Rothman2021-02-174-16/+106
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Add examples invoking FPGA interchange nextpnr.Keith Rothman2021-02-1711-0/+152
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Continue fixes.Keith Rothman2021-02-175-23/+93
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Disable traversal limit when reading logical netlist.Keith Rothman2021-02-171-1/+3
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Add initial site router.Keith Rothman2021-02-174-6/+813
| | | | | | | | This site router likely cannot handle the full problem space. It may need to be replaced with a more generalize approach as testing continues. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Working on standing up initial constraints system.Keith Rothman2021-02-173-25/+468
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* clangformatgatecat2021-02-171-3/+4
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #586 from litghost/add_cell_bel_mapping_onlygatecat2021-02-172-13/+274
|\ | | | | Add Cell -> BEL Pin maps to FPGA interchange arch.
| * Require `--package` when arch BBA contains multiple packages.Keith Rothman2021-02-161-3/+11
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * [FPGA Interchange] Add Cell -> BEL Pin maps.Keith Rothman2021-02-162-13/+266
| | | | | | | | | | | | | | This also expands the FPGA interchange Arch BBA to include placement constraints, but doesn't implement them yet. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* | Remove isValidBelForCellgatecat2021-02-162-14/+0
|/ | | | | | | | | | | | | | | | | This Arch API dates from when we were first working out how to implement placement validity checking, and in practice is little used by the core parts of placer1/HeAP and the Arch implementation involves a lot of duplication with isBelLocationValid. In the short term; placement validity checking is better served by the combination of checkBelAvail and isValidBelForCellType before placement; followed by isBelLocationValid after placement (potentially after moving/swapping multiple cells). Longer term, removing this API makes things a bit cleaner for a new validity checking API. Signed-off-by: gatecat <gatecat@ds0.me>
* Move CMake logic into fpga-interchange-schema.Keith Rothman2021-02-151-13/+1
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Small fixes from review.Keith Rothman2021-02-151-1/+1
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Add FPGA interchange frontend and backend.Keith Rothman2021-02-156-4/+914
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Merge pull request #575 from YosysHQ/gatecat/belpin-2gatecat2021-02-151-0/+3
|\ | | | | Support for cell pin to bel pin mappings
| * Add getBelPinsForCellPin to Arch APIgatecat2021-02-101-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | This is a basic implementation, without considering "M of N" arrangements (e.g. for LUT permuation where you only want to route to 1 out of 4/6 sinks) or using a type other than IdString to identify bel pins. But this is also enough to start working out where in nextpnr will break due to removing the 1:1 cell:bel pin cardinality, as a next step. Signed-off-by: gatecat <gatecat@ds0.me>
* | Run "make clangformat".Keith Rothman2021-02-124-66/+53
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* | Remove capnp and libz for XDC parser PR.Keith Rothman2021-02-121-4/+0
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* | Refactor XDC parser into a little class for testing purposes.Keith Rothman2021-02-123-14/+52
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
generated by cgit v1.2.3 (git 2.25.1) at 2025-10-31 12:39:39 +0000