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* | interchange: Debug IO port validity check failuresgatecat2021-07-122-3/+5
* | interchange: Place DIFFINBUF and IBUFCTRL for UltraScale+ IBUFDSgatecat2021-07-121-3/+4
* | interchange: update chipdb versionAlessandro Comodi2021-07-081-1/+1
* | interchange: reduce run-time to check dedicated interconnectAlessandro Comodi2021-07-084-5/+67
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* interchange: Allow pseudo pip wires to overlap with bound site wires on the s...gatecat2021-07-062-9/+5
* interchange: Improve search for PAD-attached belsgatecat2021-07-062-41/+32
* interchange: tests: add obuftds testAlessandro Comodi2021-07-066-0/+80
* interchange: phys: skip only nets writing on disconnected out portsAlessandro Comodi2021-07-021-2/+13
* Merge pull request #746 from YosysHQ/gatecat/ic-can-invert-constgatecat2021-07-011-5/+9
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| * interchange: Handle canInvert PIPs when processing preferred constantsgatecat2021-07-011-5/+9
* | interchange: Handle case where routing source is a nodegatecat2021-07-011-0/+5
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* Merge pull request #744 from YosysHQ/gatecat/const-in-macrogatecat2021-07-011-1/+1
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| * interchange: Fix handling of constants in macrosgatecat2021-07-011-1/+1
* | Merge pull request #743 from YosysHQ/gatecat/site-rsv-portsgatecat2021-07-015-0/+69
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| * | interchange: Reserve site ports only reachable from dedicated routinggatecat2021-07-015-0/+69
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* / interchange: phys: do not output nets which have no usersAlessandro Comodi2021-07-011-1/+12
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* interchange: fix dedicated interconnect explorationAlessandro Comodi2021-06-301-8/+14
* interchange: Fix dedicated interconnect check when site is the samegatecat2021-06-301-1/+4
* interchange: Place IO macro content based on routinggatecat2021-06-301-0/+79
* interchange: Track the macros that cells have been expanded fromgatecat2021-06-293-0/+8
* Merge pull request #736 from YosysHQ/gatecat/pp-multi-outputgatecat2021-06-281-13/+2
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| * interchange: Allow site wires driven by more than one belgatecat2021-06-281-13/+2
* | interchange: Handle disconnected bel pins in dedicated interconnectgatecat2021-06-281-1/+1
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* interchange: arch: move macro expansion step before ios packingAlessandro Comodi2021-06-181-1/+1
* Merge pull request #728 from YosysHQ/gatecat/nexus-ramgatecat2021-06-156-0/+382
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| * nexus: Add modified version of RAM testgatecat2021-06-155-0/+206
| * nexus: Add PDPSC16K->PDPSC16K_MODE to remap rulesgatecat2021-06-151-0/+176
* | interchange: fix phys net writerAlessandro Comodi2021-06-151-5/+2
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* interchange: Cope with undriven nets in more placesgatecat2021-06-143-5/+9
* Fixing old emails and names in copyrightsgatecat2021-06-127-9/+9
* interchange: clusters: always get cell bel map and add assertsAlessandro Comodi2021-06-111-23/+13
* interchange: run clang formatterAlessandro Comodi2021-06-112-22/+18
* interchange: clusters: adjust commentsAlessandro Comodi2021-06-112-11/+16
* interchange: increase chipinfo versionAlessandro Comodi2021-06-111-1/+1
* interchange: tests: counter: emit carries for xc7Alessandro Comodi2021-06-112-4/+6
* interchange: add support for generating BEL clustersAlessandro Comodi2021-06-119-24/+713
* fpga_interchange: Add site router testsTomasz Michalak2021-06-111-0/+3
* Remove redundant code after hashlib movegatecat2021-06-021-65/+0
* Use hashlib in most remaining codegatecat2021-06-021-2/+2
* Using hashlib in archesgatecat2021-06-0225-326/+176
* Use hashlib for core netlist structuresgatecat2021-06-025-12/+14
* Add hash() member functionsgatecat2021-06-021-0/+5
* interchange: Add LIFCL-40 EVN testsgatecat2021-06-0110-1/+82
* interchange: Add macro parameter mappinggatecat2021-05-212-3/+53
* interchange: Don't error out on missing cell portsgatecat2021-05-212-2/+3
* interchange: Add LUTRAM testgatecat2021-05-216-0/+169
* interchange: Preliminary implementation of macro expansiongatecat2021-05-213-0/+116
* interchange: Add macro param map rules to chipdbgatecat2021-05-211-0/+24
* interchange: Add macro data to chipdbgatecat2021-05-211-1/+51
* interchange: phys: add site instance idstr for pseudo tile PIPsAlessandro Comodi2021-05-191-0/+19
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