| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | refactor: New NetInfo and CellInfo constructors | gatecat | 2022-02-16 | 1 | -4/+2 |
| * | interchange: Allow site wires driven by more than one bel | gatecat | 2021-06-28 | 1 | -13/+2 |
| * | Using hashlib in arches | gatecat | 2021-06-02 | 1 | -4/+4 |
| * | interchange: pseudo pips: fix illegal tile pseudo PIPs | Alessandro Comodi | 2021-05-14 | 1 | -15/+37 |
| * | interchange: Allow pseudo-cells with no input pins | gatecat | 2021-04-13 | 1 | -14/+35 |
| * | clangformat | gatecat | 2021-04-12 | 1 | -84/+89 |
| * | [interchange] Remove requirement to have wire_lut. | Keith Rothman | 2021-04-06 | 1 | -0/+4 |
| * | [interchange] Add crude pseudo pip model. | Keith Rothman | 2021-04-06 | 1 | -0/+470 |
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index : iCE40/nextpnr | |
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