aboutsummaryrefslogtreecommitdiffstats
path: root/fpga_interchange/pseudo_pip_model.cc
Commit message (Expand)AuthorAgeFilesLines
* interchange: Allow site wires driven by more than one belgatecat2021-06-281-13/+2
* Using hashlib in archesgatecat2021-06-021-4/+4
* interchange: pseudo pips: fix illegal tile pseudo PIPsAlessandro Comodi2021-05-141-15/+37
* interchange: Allow pseudo-cells with no input pinsgatecat2021-04-131-14/+35
* clangformatgatecat2021-04-121-84/+89
* [interchange] Remove requirement to have wire_lut.Keith Rothman2021-04-061-0/+4
* [interchange] Add crude pseudo pip model.Keith Rothman2021-04-061-0/+470