| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | interchange: Handle disconnected/missing cell pins | gatecat | 2021-04-19 | 1 | -6/+0 |
| * | Add initial handling of local site inverters and constant signals. | Keith Rothman | 2021-03-25 | 1 | -7/+29 |
| * | Correct some bugs in writing of physical netlist w.r.t. site sources. | Keith Rothman | 2021-03-22 | 1 | -11/+93 |
| * | Fix compiler warnings introduced by -Wextra | gatecat | 2021-02-25 | 1 | -1/+1 |
| * | Fix assorted bugs in FPGA interchange. | Keith Rothman | 2021-02-23 | 1 | -11/+41 |
| * | Working FF example now that constant merging is done. | Keith Rothman | 2021-02-23 | 1 | -2/+11 |
| * | Add initial logic for handling dedicated interconnect situations. | Keith Rothman | 2021-02-23 | 1 | -21/+34 |
| * | Initial working constant network support! | Keith Rothman | 2021-02-23 | 1 | -9/+106 |
| * | Fix sign mismatch. | Keith Rothman | 2021-02-18 | 1 | -1/+1 |
| * | Emit fixed attributes to output physical netlist. | Keith Rothman | 2021-02-17 | 1 | -8/+19 |
| * | Continue fixes. | Keith Rothman | 2021-02-17 | 1 | -10/+49 |
| * | Disable traversal limit when reading logical netlist. | Keith Rothman | 2021-02-17 | 1 | -1/+3 |
| * | Small fixes from review. | Keith Rothman | 2021-02-15 | 1 | -1/+1 |
| * | Add FPGA interchange frontend and backend. | Keith Rothman | 2021-02-15 | 1 | -0/+826 |
