iCE40/nextpnr - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	interchange: Track the macros that cells have been expanded from	gatecat	2021-06-29	1	-0/+1
*	Fixing old emails and names in copyrights	gatecat	2021-06-12	1	-1/+1
*	Remove redundant code after hashlib move	gatecat	2021-06-02	1	-65/+0
*	Using hashlib in arches	gatecat	2021-06-02	1	-4/+3
*	Use hashlib for core netlist structures	gatecat	2021-06-02	1	-0/+2
*	Add hash() member functions	gatecat	2021-06-02	1	-0/+5
*	Add stub cluster API impl for remaining arches	gatecat	2021-05-06	1	-0/+2
*	Fixup some of the re-mapping logic.	Keith Rothman	2021-03-25	1	-3/+1
*	Add initial handling of local site inverters and constant signals.	Keith Rothman	2021-03-25	1	-0/+1
*	Rework FPGA interchange site router.	Keith Rothman	2021-03-22	1	-2/+5
*	Refactor header structures in FPGA interchange Arch.	Keith Rothman	2021-03-19	1	-2/+3
*	Split nextpnr.h to allow for linear inclusion.	Keith Rothman	2021-03-15	1	-5/+8
*	Initial LUT rotation logic.	Keith Rothman	2021-02-26	1	-0/+3
*	Working FF example now that constant merging is done.	Keith Rothman	2021-02-23	1	-0/+1
*	Replace DelayInfo with DelayPair/DelayQuad	gatecat	2021-02-19	1	-21/+0
*	Add FPGA interchange frontend and backend.	Keith Rothman	2021-02-15	1	-0/+4
*	Move all string data into BBA file.	Keith Rothman	2021-02-05	1	-18/+0
*	Update copywrite headers.	Keith Rothman	2021-02-04	1	-1/+2
*	Run "make clangformat".	Keith Rothman	2021-02-04	1	-5/+3
*	Add initial updates to FPGA interchange arch for BEL buckets.	Keith Rothman	2021-02-04	1	-0/+22
*	Initial FPGA interchange (which is just a cut-down xilinx arch).	Keith Rothman	2021-02-04	1	-0/+189