aboutsummaryrefslogtreecommitdiffstats
path: root/fpga_interchange/arch.h
Commit message (Collapse)AuthorAgeFilesLines
...
* Split nextpnr.h to allow for linear inclusion.Keith Rothman2021-03-151-7/+9
| | | | | | | | | | | | | | | | | | | "nextpnr.h" is no longer the god header. Important improvements: - Functions in log.h can be used without including BaseCtx/Arch/Context. This means that log_X functions can be called without included "nextpnr.h" - NPNR_ASSERT can be used without including "nextpnr.h" by including "nextpnr_assertions.h". This allows NPNR_ASSERT to be used safely in any header file. - Types defined in "archdefs.h" are now available without including BaseCtx/Arch/Context. This means that utility classes that will be used inside of BaseCtx/Arch/Context can be defined safely in a self-contained header. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Initial LUT rotation logic.Keith Rothman2021-02-261-1/+34
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Fix assorted bugs in FPGA interchange.Keith Rothman2021-02-231-33/+21
| | | | | | | | | | Fixes: - Only use map constant pins during routing, and not during placement. - Unmapped cell ports have no BEL pins. - Fix SiteRouter congestion not taking into account initial expansion. - Fix psuedo-site pip output. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Working FF example now that constant merging is done.Keith Rothman2021-02-231-1/+3
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Add initial logic for handling dedicated interconnect situations.Keith Rothman2021-02-231-5/+9
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Fix reference copy.Keith Rothman2021-02-231-6/+6
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Run "make clangformat".Keith Rothman2021-02-231-6/+8
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Initial working constant network support!Keith Rothman2021-02-231-4/+32
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Add initial constant network support to FPGA interchange arch.Keith Rothman2021-02-231-6/+46
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Change CellInfo in getBelPinsForCellPin to be const.Keith Rothman2021-02-231-1/+1
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Replace DelayInfo with DelayPair/DelayQuadgatecat2021-02-191-14/+4
| | | | | | | | | | | | | | | | | This replaces the arch-specific DelayInfo structure with new DelayPair (min/max only) and DelayQuad (min/max for both rise and fall) structures that form part of common code. This further reduces the amount of arch-specific code; and also provides useful data structures for timing analysis which will need to delay with pairs/quads of delays as it is improved. While there may be a small performance cost to arches that didn't separate the rise/fall cases (arches that aren't currently separating the min/max cases just need to be fixed...) in DelayInfo, my expectation is that inlining will mean this doesn't make much difference. Signed-off-by: gatecat <gatecat@ds0.me>
* Fix sign mismatch.Keith Rothman2021-02-181-1/+1
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Add some utility methods for site instance access.Keith Rothman2021-02-181-5/+37
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Refactor "get only from iterator" to a utility.Keith Rothman2021-02-171-1/+5
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Continue fixes.Keith Rothman2021-02-171-10/+3
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Add initial site router.Keith Rothman2021-02-171-4/+58
| | | | | | | | This site router likely cannot handle the full problem space. It may need to be replaced with a more generalize approach as testing continues. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Working on standing up initial constraints system.Keith Rothman2021-02-171-14/+177
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Merge pull request #586 from litghost/add_cell_bel_mapping_onlygatecat2021-02-171-6/+105
|\ | | | | Add Cell -> BEL Pin maps to FPGA interchange arch.
| * [FPGA Interchange] Add Cell -> BEL Pin maps.Keith Rothman2021-02-161-6/+105
| | | | | | | | | | | | | | This also expands the FPGA interchange Arch BBA to include placement constraints, but doesn't implement them yet. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* | Remove isValidBelForCellgatecat2021-02-161-11/+0
|/ | | | | | | | | | | | | | | | | This Arch API dates from when we were first working out how to implement placement validity checking, and in practice is little used by the core parts of placer1/HeAP and the Arch implementation involves a lot of duplication with isBelLocationValid. In the short term; placement validity checking is better served by the combination of checkBelAvail and isValidBelForCellType before placement; followed by isBelLocationValid after placement (potentially after moving/swapping multiple cells). Longer term, removing this API makes things a bit cleaner for a new validity checking API. Signed-off-by: gatecat <gatecat@ds0.me>
* Add FPGA interchange frontend and backend.Keith Rothman2021-02-151-0/+10
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Merge pull request #575 from YosysHQ/gatecat/belpin-2gatecat2021-02-151-0/+3
|\ | | | | Support for cell pin to bel pin mappings
| * Add getBelPinsForCellPin to Arch APIgatecat2021-02-101-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | This is a basic implementation, without considering "M of N" arrangements (e.g. for LUT permuation where you only want to route to 1 out of 4/6 sinks) or using a type other than IdString to identify bel pins. But this is also enough to start working out where in nextpnr will break due to removing the 1:1 cell:bel pin cardinality, as a next step. Signed-off-by: gatecat <gatecat@ds0.me>
* | Add FPGA interchange XDC parser.Keith Rothman2021-02-121-1/+4
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* | Add getBelHidden and add some missing "override" statements.Keith Rothman2021-02-111-2/+1
|/ | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* interchange: Base on ArchAPID. Shah2021-02-081-103/+134
| | | | Signed-off-by: D. Shah <dave@ds0.me>
* Add RelSlice::ssize and use it when comparing with signed ints.Keith Rothman2021-02-051-13/+14
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Move all string data into BBA file.Keith Rothman2021-02-051-6/+7
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Use RelSlice instead of RelPtr in cases where sizes are present.Keith Rothman2021-02-041-80/+50
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Update APIs to conform to style guide.Keith Rothman2021-02-041-52/+55
| | | | | | | - Change non-Arch methods to snake_case - Adds some utility functions to for accessing bel_data. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Remove unused method getReservedWireNet.Keith Rothman2021-02-041-7/+0
| | | | | | This was a holdover from the nextpnr-xilinx arch. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Update copywrite headers.Keith Rothman2021-02-041-1/+2
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Run "make clangformat".Keith Rothman2021-02-041-104/+73
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Update FPGA interchange to use IdStringList.Keith Rothman2021-02-041-32/+25
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Start adding data for placement constraint solving.Keith Rothman2021-02-041-5/+22
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Debug BEL bucket data.Keith Rothman2021-02-041-11/+14
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Add initial updates to FPGA interchange arch for BEL buckets.Keith Rothman2021-02-041-0/+204
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Address review comments.Keith Rothman2021-02-041-0/+1
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Fix BBA import bugs.Keith Rothman2021-02-041-21/+46
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Assorted fixes to new FPGA interchange based arch.Keith Rothman2021-02-041-1/+1
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Initial compiling version.Keith Rothman2021-02-041-16/+16
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Initial FPGA interchange (which is just a cut-down xilinx arch).Keith Rothman2021-02-041-0/+1096
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-05 02:48:17 +0000