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* Fixing old emails and names in copyrightsgatecat2021-06-121-2/+2
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* interchange: run clang formatterAlessandro Comodi2021-06-111-1/+1
| | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* interchange: add support for generating BEL clustersAlessandro Comodi2021-06-111-14/+41
| | | | | | | | Clustering greatly helps the placer to identify and pack together specific cells at the same site (e.g. LUT+FF), or cells that are chained through dedicated interconnections (e.g. CARRY CHAINS) Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* Using hashlib in archesgatecat2021-06-021-11/+11
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* interchange: Preliminary implementation of macro expansiongatecat2021-05-211-0/+2
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* interchange: Adding a basic global buffer placergatecat2021-05-071-0/+2
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* interchange: Initial global routing implementationgatecat2021-05-071-0/+6
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Add stub cluster API impl for remaining archesgatecat2021-05-061-0/+13
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* interchange: Handle disconnected/missing cell pinsgatecat2021-04-191-0/+3
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* clangformatgatecat2021-04-121-3/+3
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* [interchange] Remove requirement to have wire_lut.Keith Rothman2021-04-061-0/+3
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* [interchange] Scale edge cost of pseudo pips.Keith Rothman2021-04-061-5/+1
| | | | | | | Previous pseudo pips were the same cost as regular pips, but this is definitely too fast, and meant that the router was prefering them. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* [interchange] Disallow site edges during general routing.Keith Rothman2021-04-061-0/+1
| | | | | | | This prevents the general router from routing through sites, which is not legal in FPGA interchange. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* [interchange] Add crude pseudo pip model.Keith Rothman2021-04-061-2/+14
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* interchange: Fix illegal placementsgatecat2021-03-301-6/+5
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Implement debugging tools for site router.Keith Rothman2021-03-251-0/+2
| | | | | | | | - Finishes implementation of SiteArch::nameOfPip and SiteArch::nameOfWire - Adds "explain_bel_status", which should be an exhaustive diagnostic of the status of a BEL placement. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Re-work LUT mapping logic to only put VCC pins when required.Keith Rothman2021-03-251-1/+0
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Add initial handling of local site inverters and constant signals.Keith Rothman2021-03-251-0/+13
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* [FPGA interchange] Small fix to get_net_type.Keith Rothman2021-03-251-3/+8
| | | | | | | If get_net_type was called before the driver was placed, it could return the wrong value. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Merge pull request #644 from litghost/add_global_buffersgatecat2021-03-231-1/+13
|\ | | | | [FPGA interchange] Add support for global buffers from chipdb.
| * [FPGA interchange] Add support for global buffers from chipdb.Keith Rothman2021-03-231-1/+13
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* | Merge pull request #643 from litghost/id_constantsgatecat2021-03-231-0/+2
|\ \ | |/ |/| [FPGA interchange] Convert some string constants to IdString.
| * [FPGA interchange] Convert some string constants to IdString.Keith Rothman2021-03-231-0/+2
| | | | | | | | | | | | Also add some optional diagnostic prints for cell -> BEL pin mapping. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* | Initial version of inverter logic.Keith Rothman2021-03-231-0/+6
| | | | | | | | | | | | | | For now just implements some inspection capabilities, and the site router (for now) avoids inverted paths. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* | Use new parameter definition data in FPGA interchange processing.Keith Rothman2021-03-231-0/+2
|/ | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Initial lookahead for FPGA interchange.Keith Rothman2021-03-231-0/+8
| | | | | | | | | Currently the lookahead is disabled by default because of the time to compute and RAM usage. However it does appear to work reasonably well in testing. Further effort is required to lower RAM usage after initial computation, and explore trade-off for cheaper time to compute. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Merge pull request #637 from litghost/refine_site_routergatecat2021-03-221-0/+3
|\ | | | | Refine site router
| * Rework FPGA interchange site router.Keith Rothman2021-03-221-0/+3
| | | | | | | | | | | | | | The new site router should be robust to most situations, and isn't significantly slower with the use of caching. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* | Add "checkPipAvailForNet" to Arch API.Keith Rothman2021-03-221-1/+1
|/ | | | | | | | This is important for distiguishing valid pseudo pips in the FPGA interchange arch. This also avoids a double or triple lookup of pip->net map. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Add pseudo pip data to chipdb (with schema bump).Keith Rothman2021-03-221-0/+14
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Refactor header structures in FPGA interchange Arch.Keith Rothman2021-03-191-876/+160
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Use NEXTPNR_NAMESPACE macro's now that headers are seperated.Keith Rothman2021-03-151-1/+1
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Split nextpnr.h to allow for linear inclusion.Keith Rothman2021-03-151-7/+9
| | | | | | | | | | | | | | | | | | | "nextpnr.h" is no longer the god header. Important improvements: - Functions in log.h can be used without including BaseCtx/Arch/Context. This means that log_X functions can be called without included "nextpnr.h" - NPNR_ASSERT can be used without including "nextpnr.h" by including "nextpnr_assertions.h". This allows NPNR_ASSERT to be used safely in any header file. - Types defined in "archdefs.h" are now available without including BaseCtx/Arch/Context. This means that utility classes that will be used inside of BaseCtx/Arch/Context can be defined safely in a self-contained header. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Initial LUT rotation logic.Keith Rothman2021-02-261-1/+34
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Fix assorted bugs in FPGA interchange.Keith Rothman2021-02-231-33/+21
| | | | | | | | | | Fixes: - Only use map constant pins during routing, and not during placement. - Unmapped cell ports have no BEL pins. - Fix SiteRouter congestion not taking into account initial expansion. - Fix psuedo-site pip output. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Working FF example now that constant merging is done.Keith Rothman2021-02-231-1/+3
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Add initial logic for handling dedicated interconnect situations.Keith Rothman2021-02-231-5/+9
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Fix reference copy.Keith Rothman2021-02-231-6/+6
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Run "make clangformat".Keith Rothman2021-02-231-6/+8
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Initial working constant network support!Keith Rothman2021-02-231-4/+32
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Add initial constant network support to FPGA interchange arch.Keith Rothman2021-02-231-6/+46
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Change CellInfo in getBelPinsForCellPin to be const.Keith Rothman2021-02-231-1/+1
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Replace DelayInfo with DelayPair/DelayQuadgatecat2021-02-191-14/+4
| | | | | | | | | | | | | | | | | This replaces the arch-specific DelayInfo structure with new DelayPair (min/max only) and DelayQuad (min/max for both rise and fall) structures that form part of common code. This further reduces the amount of arch-specific code; and also provides useful data structures for timing analysis which will need to delay with pairs/quads of delays as it is improved. While there may be a small performance cost to arches that didn't separate the rise/fall cases (arches that aren't currently separating the min/max cases just need to be fixed...) in DelayInfo, my expectation is that inlining will mean this doesn't make much difference. Signed-off-by: gatecat <gatecat@ds0.me>
* Fix sign mismatch.Keith Rothman2021-02-181-1/+1
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Add some utility methods for site instance access.Keith Rothman2021-02-181-5/+37
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Refactor "get only from iterator" to a utility.Keith Rothman2021-02-171-1/+5
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Continue fixes.Keith Rothman2021-02-171-10/+3
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Add initial site router.Keith Rothman2021-02-171-4/+58
| | | | | | | | This site router likely cannot handle the full problem space. It may need to be replaced with a more generalize approach as testing continues. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Working on standing up initial constraints system.Keith Rothman2021-02-171-14/+177
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Merge pull request #586 from litghost/add_cell_bel_mapping_onlygatecat2021-02-171-6/+105
|\ | | | | Add Cell -> BEL Pin maps to FPGA interchange arch.
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