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* | ecp5: Working on DCUDavid Shah2018-11-153-5/+63
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | ecp5: DCU bitstream gen handlingDavid Shah2018-11-152-0/+299
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | ecp5: Groundwork for DCU supportDavid Shah2018-11-153-16/+318
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | Merge remote-tracking branch 'origin/master' into timingapiEddie Hung2018-11-134-3/+11
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| * \ Merge pull request #107 from YosysHQ/router_improveEddie Hung2018-11-133-2/+10
| |\ \ | | | | | | | | Major rewrite of "router1"
| | * | ecp5: Improve delay estimatesDavid Shah2018-11-131-2/+2
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| | * | Various router1 fixes, Add BelId/WireId/PipId::operator<()Clifford Wolf2018-11-131-0/+4
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * | clangformatClifford Wolf2018-11-111-8/+2
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * | Add getConflictingWireWire() arch API, streamline getConflictingXY semanticClifford Wolf2018-11-111-5/+10
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * | Add getConflictingPipWire() arch API, router1 improvementsClifford Wolf2018-11-111-0/+5
| | |/ | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Mark getArchOptions as override in derived classesPedro Vanzella2018-11-131-1/+1
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* | | ecp5: Copy clock constraints during global promotionDavid Shah2018-11-121-0/+7
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | timing: Add support for clock constraintsDavid Shah2018-11-121-0/+4
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | ecp5: EBR clocking fixDavid Shah2018-11-121-5/+8
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | ecp5: Update arch to new timing APIDavid Shah2018-11-122-15/+72
|/ / | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | ecp5: Fix 85k PLL_LRDavid Shah2018-11-111-1/+2
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | show 4th tresllis_io in tile boundsMiodrag Milanovic2018-11-111-1/+1
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* ecp5: Allow setting IO SLEWRATEDavid Shah2018-11-011-0/+2
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Add PLL supportDavid Shah2018-10-314-7/+168
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Separate global promotion and routingDavid Shah2018-10-314-33/+87
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Add IO buffer insertionDavid Shah2018-10-314-15/+70
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Adding LPF parserDavid Shah2018-10-313-0/+122
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: DSP fixesDavid Shah2018-10-222-33/+42
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* ecp5: Working on DSPsDavid Shah2018-10-222-83/+200
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* ecp5: Adding DSP supportDavid Shah2018-10-213-1/+799
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* ecp5: Implement ECP5 equivalent of c9059fcDavid Shah2018-10-211-0/+9
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* clangformatDavid Shah2018-10-162-5/+9
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Add support for correct tile naming in all variantsDavid Shah2018-10-164-4/+84
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Add DP16KD timing analysisDavid Shah2018-10-161-2/+29
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Optimise DCC placementDavid Shah2018-10-141-3/+12
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* ecp5: Fix BRAM tile namesDavid Shah2018-10-111-1/+1
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Fixing BRAM initialisationDavid Shah2018-10-101-4/+14
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Working on BRAM initialisationDavid Shah2018-10-093-0/+82
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: BRAM improvements with constant/inverted inputsDavid Shah2018-10-062-14/+80
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Fixing EBR constant tie-offsDavid Shah2018-10-052-1/+51
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Bitstream gen for DP16KD BRAMDavid Shah2018-10-051-0/+98
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Infrastructure for BRAM bitstream genDavid Shah2018-10-053-0/+56
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Dummy timing entry for BRAMDavid Shah2018-10-051-0/+3
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Adding constids for blockramDavid Shah2018-10-051-0/+118
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Negative clock support, general slice improvementsDavid Shah2018-10-023-4/+41
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* ecp5: Small DRAM routing fixesDavid Shah2018-10-012-7/+25
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* clangformatDavid Shah2018-10-013-6/+4
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* ecp5: Fix packing of FFs into carry/DRAM slicesDavid Shah2018-10-011-4/+12
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* ecp5: Fix DRAM initialisationDavid Shah2018-10-011-2/+2
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* ecp5: Remove broken DRAM timing arcDavid Shah2018-10-011-2/+2
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* ecp5: Debugging DRAM packingDavid Shah2018-10-013-6/+17
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* ecp5: Working on DRAM packingDavid Shah2018-10-012-1/+68
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* ecp5: Handling of DRAM initialisation and wiringDavid Shah2018-10-011-1/+59
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* ecp5: Helper functions for distributed RAM supportDavid Shah2018-10-013-0/+64
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* ecp5: Improve handling of constant CCU2C inputsDavid Shah2018-10-011-9/+65
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
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