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| author | David Shah <dave@ds0.me> | 2018-10-05 11:35:37 +0100 |
|---|---|---|
| committer | David Shah <dave@ds0.me> | 2018-10-05 11:35:37 +0100 |
| commit | 19f828c91c836a6d8e04676ca76ec2c6d0004b8a (patch) | |
| tree | 4c6e01076d5eeee08e7ba29a2c85c87e4da8fc80 /ecp5 | |
| parent | 48f08e6d395be4ed7436150ad5e45a14c981e0be (diff) | |
| download | nextpnr-19f828c91c836a6d8e04676ca76ec2c6d0004b8a.tar.gz nextpnr-19f828c91c836a6d8e04676ca76ec2c6d0004b8a.tar.bz2 nextpnr-19f828c91c836a6d8e04676ca76ec2c6d0004b8a.zip | |
ecp5: Dummy timing entry for BRAM
Signed-off-by: David Shah <dave@ds0.me>
Diffstat (limited to 'ecp5')
| -rw-r--r-- | ecp5/arch.cc | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/ecp5/arch.cc b/ecp5/arch.cc index 9c059005..b3a40a03 100644 --- a/ecp5/arch.cc +++ b/ecp5/arch.cc @@ -582,6 +582,9 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, Id if (port == id_CLKO) return TMG_COMB_OUTPUT; return TMG_IGNORE; + } else if (cell->type == id_DP16KD) { + // FIXME + return TMG_IGNORE; } else { NPNR_ASSERT_FALSE_STR("no timing data for cell type '" + cell->type.str(this) + "'"); } |