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* Initial conversion to pybind11Miodrag Milanovic2020-07-231-18/+16
* ecp5: Add a warning for unknown LPF IOBUF attrsDavid Shah2020-07-131-0/+8
* ecp5: Add SYSCONFIG settings to bitstreamDavid Shah2020-07-124-3/+38
* ecp5: Add parsing of SYSCONFIG line in LPFDavid Shah2020-07-121-1/+20
* Merge pull request #463 from YosysHQ/fix-archcheckDavid Shah2020-07-021-2/+3
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| * ecp5: Fix getTileBelDimZDavid Shah2020-06-291-2/+3
* | CMake: improve logic for discovering Trellis.whitequark2020-07-011-1/+25
* | CMake: fix path checks in chipdb build scripts.whitequark2020-07-011-2/+2
* | ecp5: Fix derivation of OSCG timing constraintDavid Shah2020-06-291-1/+5
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* Fix clangformat and execute itMiodrag Milanovic2020-06-271-12/+8
* Update git ignore locationsMiodrag Milanovic2020-06-271-1/+1
* Merge pull request #460 from whitequark/better-embedDavid Shah2020-06-268-109/+66
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| * Simplify and improve chipdb embedding/loading.whitequark2020-06-268-109/+66
* | Fix typowhitequark2020-06-251-1/+1
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* CMake: require at least version 3.5 (Ubuntu 16.04).whitequark2020-06-251-1/+1
* CMake: rewrite chipdb handling from ground up.whitequark2020-06-256-119/+151
* ecp5: Fix placement of DCCs to guarantee routeabilityDavid Shah2020-06-101-2/+44
* Merge pull request #447 from whitequark/wasiDavid Shah2020-05-242-8/+18
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| * Port nextpnr-{ice40,ecp5} to WASI.whitequark2020-05-232-8/+18
* | Merge pull request #440 from YosysHQ/lattice-fixesDavid Shah2020-05-183-0/+28
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| * | ecp5: Disconnect dedicated DCU inputs if connected to constantsDavid Shah2020-05-141-0/+12
| * | ecp5: Improve global routing robustnessDavid Shah2020-05-141-0/+11
| * | ecp5: Don't promote VCC/GND to globals even if connected to clock portDavid Shah2020-05-141-0/+2
| * | lpf: Support // commentsDavid Shah2020-05-141-0/+3
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* | clangformatDavid Shah2020-05-161-1/+2
* | Merge pull request #442 from nategraff-sifive/fix-unsupported-spellingDavid Shah2020-05-141-5/+5
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| * Fix spelling of 'unsupported'Nathaniel Graff2020-05-131-5/+5
* | ecp5: Allow setting drive strength for LVCMOS33D IOsMike Walters2020-05-121-0/+19
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* ecp5: MULT18X18D timing fixesDavid Shah2020-05-011-10/+26
* No cell delay for clocked MULT18X18DRoss Schlaikjer2020-04-301-0/+2
* Further condenseRoss Schlaikjer2020-04-291-11/+10
* Dedupe clock error checkRoss Schlaikjer2020-04-291-12/+13
* Issue warning for mixed-mode inputsRoss Schlaikjer2020-04-293-40/+46
* Handle register timing caseRoss Schlaikjer2020-04-291-6/+58
* Use registered port class on mult18x18Ross Schlaikjer2020-04-291-3/+5
* Alter MULT18X18D timing db based on register configRoss Schlaikjer2020-04-283-2/+43
* ecp5: Fix CSDECODE bitgenDavid Shah2020-04-151-0/+3
* ecp5: Use dedicated routing for ECLKs where possibleDavid Shah2020-04-141-1/+80
* Add TRELLIS_PROGRAM_PREFIXMiodrag Milanovic2020-04-111-4/+6
* ecp5: Fix routing bitgen for non-SERDES 'VCIB' tilesDavid Shah2020-04-101-3/+12
* ecp5: Make hysteresis default-on for LVCMOS33 bidir as well as inputDavid Shah2020-04-091-9/+7
* Merge pull request #423 from rschlaikjer/rschlaikjer-regmode-timing-databaseDavid Shah2020-04-073-4/+33
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| * No need to fetch contextRoss Schlaikjer2020-04-071-3/+2
| * Change assert to errorRoss Schlaikjer2020-04-071-2/+5
| * Rearrange bool algebraRoss Schlaikjer2020-04-071-2/+2
| * Actually just move all the logic to ArchInfoRoss Schlaikjer2020-04-073-19/+23
| * Extract regmode configuration to ArchInfoRoss Schlaikjer2020-04-073-8/+16
| * Change timing database lookup based on REGMODE valueRoss Schlaikjer2020-04-071-4/+19
* | Merge pull request #419 from garytwong/handle-opendrainDavid Shah2020-04-071-0/+3
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| * | Handle OPENDRAIN attribute.Gary Wong2020-04-031-0/+3
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