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* clangformatDavid Shah2018-11-162-172/+342
* Merge pull request #119 from cr1901/win-fixDavid Shah2018-11-164-2/+6
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| * Use native PATH environment-variable separator on Windows for PYTHONPATH. Fix...William D. Jones2018-11-031-0/+4
| * Rename io.{h,cc} to pio.{h,cc} to avoid naming conflict with Windows-provided...William D. Jones2018-11-033-2/+2
* | ecp5: Better use of BoostDavid Shah2018-11-161-3/+3
* | ecp5: Regression fix & formatDavid Shah2018-11-152-4/+14
* | ecp5: Support LOC attribute on DCUsDavid Shah2018-11-151-1/+25
* | ecp5: Add DCU availability checkDavid Shah2018-11-151-0/+2
* | ecp5: Add timing info for SERDESDavid Shah2018-11-151-1/+26
* | ecp5: DCU clocking fixesDavid Shah2018-11-151-2/+8
* | ecp5: EXTREFB fixesDavid Shah2018-11-152-1/+5
* | ecp5: clangformatDavid Shah2018-11-152-18/+23
* | ecp5: Trim IO connected to top level portsDavid Shah2018-11-151-15/+73
* | ecp5: Adding ancillary DCU belsDavid Shah2018-11-154-1/+57
* | ecp5: remove debug and clangformatDavid Shah2018-11-153-10/+13
* | dcu: Fix bitstream param handlingDavid Shah2018-11-151-0/+1
* | ecp5: Prefer DCCs with dedicated routing when placing DCCsDavid Shah2018-11-151-0/+43
* | ecp5: Working on DCUDavid Shah2018-11-153-5/+63
* | ecp5: DCU bitstream gen handlingDavid Shah2018-11-152-0/+299
* | ecp5: Groundwork for DCU supportDavid Shah2018-11-153-16/+318
* | Merge remote-tracking branch 'origin/master' into timingapiEddie Hung2018-11-134-3/+11
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| * \ Merge pull request #107 from YosysHQ/router_improveEddie Hung2018-11-133-2/+10
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| | * | ecp5: Improve delay estimatesDavid Shah2018-11-131-2/+2
| | * | Various router1 fixes, Add BelId/WireId/PipId::operator<()Clifford Wolf2018-11-131-0/+4
| | * | clangformatClifford Wolf2018-11-111-8/+2
| | * | Add getConflictingWireWire() arch API, streamline getConflictingXY semanticClifford Wolf2018-11-111-5/+10
| | * | Add getConflictingPipWire() arch API, router1 improvementsClifford Wolf2018-11-111-0/+5
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| * | Mark getArchOptions as override in derived classesPedro Vanzella2018-11-131-1/+1
* | | ecp5: Copy clock constraints during global promotionDavid Shah2018-11-121-0/+7
* | | timing: Add support for clock constraintsDavid Shah2018-11-121-0/+4
* | | ecp5: EBR clocking fixDavid Shah2018-11-121-5/+8
* | | ecp5: Update arch to new timing APIDavid Shah2018-11-122-15/+72
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* | ecp5: Fix 85k PLL_LRDavid Shah2018-11-111-1/+2
* | show 4th tresllis_io in tile boundsMiodrag Milanovic2018-11-111-1/+1
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* ecp5: Allow setting IO SLEWRATEDavid Shah2018-11-011-0/+2
* ecp5: Add PLL supportDavid Shah2018-10-314-7/+168
* ecp5: Separate global promotion and routingDavid Shah2018-10-314-33/+87
* ecp5: Add IO buffer insertionDavid Shah2018-10-314-15/+70
* ecp5: Adding LPF parserDavid Shah2018-10-313-0/+122
* ecp5: DSP fixesDavid Shah2018-10-222-33/+42
* ecp5: Working on DSPsDavid Shah2018-10-222-83/+200
* ecp5: Adding DSP supportDavid Shah2018-10-213-1/+799
* ecp5: Implement ECP5 equivalent of c9059fcDavid Shah2018-10-211-0/+9
* clangformatDavid Shah2018-10-162-5/+9
* ecp5: Add support for correct tile naming in all variantsDavid Shah2018-10-164-4/+84
* ecp5: Add DP16KD timing analysisDavid Shah2018-10-161-2/+29
* ecp5: Optimise DCC placementDavid Shah2018-10-141-3/+12
* ecp5: Fix BRAM tile namesDavid Shah2018-10-111-1/+1
* ecp5: Fixing BRAM initialisationDavid Shah2018-10-101-4/+14
* ecp5: Working on BRAM initialisationDavid Shah2018-10-093-0/+82
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