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* ecp5: Router2 test integrationDavid Shah2020-02-031-1/+38
* Merge remote-tracking branch 'origin/master' into mmicko/ecp5_guiMiodrag Milanovic2019-12-281-1/+11
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| * ecp5: Add an error for out-of-sync constids and bbaDavid Shah2019-10-261-0/+3
| * ecp5: Fix routing to shared DSP control inputsDavid Shah2019-10-251-1/+8
* | move bel creation to gfx.ccMiodrag Milanovic2019-12-151-122/+2
* | fix formatingMiodrag Milanovic2019-12-141-2/+1
* | more new wires addedMiodrag Milanovic2019-12-141-1/+10
* | ebr, mult and alu nice displayMiodrag Milanovic2019-12-141-1/+1
* | clangformat runMiodrag Milanovic2019-12-081-27/+30
* | display IOs properlyMiodrag Milanovic2019-12-071-21/+5
* | More bels show properlyMiodrag Milanovic2019-12-071-43/+82
* | add dcca bels and dummy parts for other belsMiodrag Milanovic2019-12-071-9/+54
* | more pips, and valid mappingMiodrag Milanovic2019-11-101-4/+4
* | Draw some pips, fixed H6 and V6Miodrag Milanovic2019-11-091-1/+22
* | Show V02/V06/H02/H06Miodrag Milanovic2019-10-251-1/+1
* | Split graphics calls for wires into gfx.ccMiodrag Milanovic2019-10-201-268/+3
* | muxes only together with slicesMiodrag Milanovic2019-10-201-9/+7
* | Remove not used lineMiodrag Milanovic2019-10-201-2/+0
* | Simplify layout of elementsMiodrag Milanovic2019-10-201-170/+114
* | fix slice wireMiodrag Milanovic2019-10-201-20/+20
* | bound signalsMiodrag Milanovic2019-10-201-0/+65
* | more wires between switchboxesMiodrag Milanovic2019-10-201-1/+37
* | Add more types of wiresMiodrag Milanovic2019-10-201-176/+191
* | finixed slice wiresMiodrag Milanovic2019-10-201-0/+27
* | wd wiresMiodrag Milanovic2019-10-201-1/+21
* | Fix look of some wiresMiodrag Milanovic2019-10-201-6/+9
* | Add output wiresMiodrag Milanovic2019-10-201-0/+35
* | fix mux displayMiodrag Milanovic2019-10-201-2/+2
* | set wire active flagMiodrag Milanovic2019-10-201-1/+1
* | clk and lsr muxesMiodrag Milanovic2019-10-201-1/+62
* | draw rest of slice wires and more from switchboxMiodrag Milanovic2019-10-201-3/+52
* | OptimizeMiodrag Milanovic2019-10-201-12/+4
* | Add other side of slice wiresMiodrag Milanovic2019-10-201-9/+24
* | Display rest of slice input wiresMiodrag Milanovic2019-10-201-2/+8
* | Start adding visible wiresMiodrag Milanovic2019-10-201-1/+38
* | Draw swbox, smaller slices, proper ioMiodrag Milanovic2019-10-201-10/+113
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* ecp5: Preparations for new IO belsDavid Shah2019-10-091-0/+4
* ecp5: Adding support for 36-bit wide PDP RAMsDavid Shah2019-10-011-4/+17
* ecp5: Add full part name to bitstream headerDavid Shah2019-08-271-0/+20
* ecp5: Add GSR/SGSR supportDavid Shah2019-08-271-2/+6
* Merge pull request #309 from YosysHQ/dsptimingDavid Shah2019-08-091-1/+17
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| * ecp5: Conservative analysis of comb DSP timingDavid Shah2019-07-081-1/+17
* | ecp5: Add --out-of-context for building hard macrosDavid Shah2019-08-071-1/+7
* | ecp5: New Property interfaceDavid Shah2019-08-051-2/+2
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* Merge masterMiodrag Milanovic2019-06-251-3/+5
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| * ecp5: Delay tweaking for lower speed gradesDavid Shah2019-06-211-2/+4
| * ecp5: Reduce cfg.criticalityExponent for nowDavid Shah2019-06-211-1/+1
* | Use flags for each stepMiodrag Milanovic2019-06-141-2/+2
* | Save top level attrs and store current stepMiodrag Milanovic2019-06-071-0/+2
* | CleanupMiodrag Milanovic2019-06-071-11/+0