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* Run "make clangformat" to fix new Bits library.Keith Rothman2021-02-232-11/+16
* Demote the 'no clocks' warning to info and make clearergatecat2021-02-201-1/+1
* Merge pull request #592 from YosysHQ/gatecat/rework-delaygatecat2021-02-207-35/+98
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| * python: Bindings for DelayPair and DelayQuadgatecat2021-02-191-0/+25
| * Replace DelayInfo with DelayPair/DelayQuadgatecat2021-02-196-35/+38
| * Add DelayPair and DelayQuad structuresgatecat2021-02-191-0/+35
* | clangformatgatecat2021-02-191-1/+2
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* Merge pull request #576 from litghost/add_cell_bel_pin_mappinggatecat2021-02-196-0/+443
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| * Use Bits library for bit instrisics.Keith Rothman2021-02-171-2/+4
| * Refactor "get only from iterator" to a utility.Keith Rothman2021-02-171-0/+23
| * Working on standing up initial constraints system.Keith Rothman2021-02-175-0/+418
* | Expose ice40 arch placer-heap internal parameters.Balint Cristian2021-02-182-4/+32
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* Add a Bits utility library.Keith Rothman2021-02-172-0/+124
* Remove isValidBelForCellgatecat2021-02-164-24/+38
* Merge pull request #575 from YosysHQ/gatecat/belpin-2gatecat2021-02-155-173/+253
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| * router2: Support for multiple bel pins per cell pingatecat2021-02-101-85/+95
| * router1: Support for multiple bel pins per cell pingatecat2021-02-101-62/+78
| * Start making use of getBelPinsForCellPin APIgatecat2021-02-105-37/+83
| * Add getBelPinsForCellPin to Arch APIgatecat2021-02-101-0/+8
* | Merge pull request #579 from litghost/add_control_for_split_iogatecat2021-02-121-0/+1
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| * | Add control to whether GenericFrontend splits IO ports.Keith Rothman2021-02-111-0/+1
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* | Make BaseArch getDecalGraphics return an empty rangegatecat2021-02-121-1/+1
* | Merge pull request #580 from litghost/add_design_loaded_state_variablegatecat2021-02-122-1/+6
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| * | Add design_loaded state variable.Keith Rothman2021-02-112-1/+6
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* / Add getBelHidden and add some missing "override" statements.Keith Rothman2021-02-112-3/+8
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* Remove the unused CellInfo::pins fieldgatecat2021-02-103-25/+0
* Add BaseArchRanges for default ArchRanges typesgatecat2021-02-091-0/+21
* Make BaseCtx destructor virtualgatecat2021-02-081-1/+1
* Use 'T' postfix to disambiguate LHS and RHS of usingD. Shah2021-02-081-42/+48
* Add archArgs and archArgsToId to Arch APID. Shah2021-02-051-0/+3
* ice40: Switch to BaseArchD. Shah2021-02-051-0/+1
* Add pure-virtual ArchAPI interfaceD. Shah2021-02-051-104/+198
* Rename ArchBase to BaseArch for consistency with BaseCtxD. Shah2021-02-051-1/+1
* Add default implementation of bel bucket functionsD. Shah2021-02-051-5/+89
* Add default implementation of some range-returning functionsD. Shah2021-02-051-5/+27
* Add a few more functions to ArchBaseD. Shah2021-02-051-8/+14
* ecp5: Use common wire/pip bindingD. Shah2021-02-051-1/+1
* Fix now-illegal use of reinterpret_castD. Shah2021-02-051-3/+5
* nextpnr: Example of shared wire/bel/pip binding codeD. Shah2021-02-051-13/+106
* nextpnr: Use templates to specify range typesD. Shah2021-02-051-0/+21
* nextpnr: Add base virtual functions for non-range Arch APID. Shah2021-02-051-0/+108
* Add RelSlice::ssize and use it when comparing with signed ints.Keith Rothman2021-02-051-0/+1
* Mark IdString and IdStringList single argument constructors explicit.Keith Rothman2021-02-043-18/+28
* Use a LRU cache for pip to wire map.Keith Rothman2021-02-031-10/+113
* generic: Use IdStringList for all arch object namesD. Shah2021-02-023-1/+28
* nexus: Implement IdStringList for all arch object namesD. Shah2021-02-021-0/+6
* ecp5: Implement IdStringList for all arch object namesD. Shah2021-02-023-8/+55
* refactor: Replace getXName().c_str(ctx) with ctx->nameOfXD. Shah2021-02-023-9/+8
* ecp5: Proof-of-concept using IdStringList for bel namesD. Shah2021-02-027-24/+56
* common: First pass at IdStringList methodsD. Shah2021-02-022-3/+64
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