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* mistral: Tidying upgatecat2021-05-152-2/+3
* router2: Hacky workaround for slow Cyclone V convergencegatecat2021-05-151-3/+3
* router2: Reduce verbosity when debugginggatecat2021-05-151-0/+2
* mistral: Add stub pack/place/route functionsgatecat2021-05-151-1/+1
* archcheck: Use old connectivity check for CycloneVgatecat2021-05-151-1/+29
* cyclonev: Add names and archcheck fixesgatecat2021-05-152-0/+22
* router2: Add some boundness statisticsgatecat2021-05-121-0/+33
* router2: Fix a typogatecat2021-05-111-1/+1
* command: Allow debug output for just placer or routergatecat2021-05-111-0/+11
* router2: Reserve wires in more complex casesgatecat2021-05-061-13/+39
* router2: Dynamicly expand bounding box based on congestiongatecat2021-05-061-10/+22
* Add stub cluster API impl for remaining archesgatecat2021-05-061-0/+2
* base_arch: Fix typo in getClusterPlacementgatecat2021-05-061-1/+1
* Update placers to use new cluster APIsgatecat2021-05-069-344/+149
* Add default base implementation of cluster APIgatecat2021-05-063-5/+97
* Add BaseClusterInfo for base implementationgatecat2021-05-061-0/+44
* arch_api: Outline of new cluster APIgatecat2021-05-062-9/+9
* Update bits.hDavid Corrigan2021-04-301-2/+2
* interchange: Implement getWireTypegatecat2021-04-301-0/+2
* Merge pull request #681 from YosysHQ/gatecat/more-pybindingsgatecat2021-04-151-0/+3
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| * Add Python bindings for placement testsgatecat2021-04-151-0/+3
* | Fix utilisation report when bel buckets are usedgatecat2021-04-151-2/+2
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* Hash table refactoringgatecat2021-04-142-50/+28
* timing: Fix domain init when loops are presentgatecat2021-04-132-58/+73
* Merge pull request #674 from adamgreig/heap-spreader-fixgatecat2021-04-121-0/+4
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| * HeAP: Skip high-strength cells in both cell loops.Adam Greig2021-04-121-0/+4
* | fast_bels: Don't return pointer that might become invalidgatecat2021-04-121-14/+18
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* Fix bug in router2 where router may give up too early.Keith Rothman2021-04-061-1/+13
* interchange: Fix illegal placementsgatecat2021-03-301-1/+3
* Add initial handling of local site inverters and constant signals.Keith Rothman2021-03-251-2/+3
* Use new parameter definition data in FPGA interchange processing.Keith Rothman2021-03-232-1/+130
* Merge pull request #634 from litghost/add_get_bel_pin_typegatecat2021-03-221-0/+2
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| * Add getBelPinType to Python interface.Keith Rothman2021-03-221-0/+2
* | Add "checkPipAvailForNet" to Arch API.Keith Rothman2021-03-223-13/+13
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* Refactor header structures in FPGA interchange Arch.Keith Rothman2021-03-191-0/+3
* Run "make clangformat". to fix up master.Keith Rothman2021-03-184-4/+3
* Moving hash map/set type selection to header.Keith Rothman2021-03-172-8/+52
* Add missing includes to fix WASI build.whitequark2021-03-162-0/+5
* Use NEXTPNR_NAMESPACE macro's now that headers are seperated.Keith Rothman2021-03-159-23/+29
* Merge pull request #621 from litghost/fix_header_nightmaregatecat2021-03-1530-2395/+3104
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| * Split nextpnr.h to allow for linear inclusion.Keith Rothman2021-03-1530-2395/+3104
* | opt-timing: Skip undriven netsgatecat2021-03-151-0/+2
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* Add support for partially routed nets from the placer in router2.Keith Rothman2021-03-122-28/+54
* Add diagnostic prints to debug lookahead performance.Keith Rothman2021-03-101-13/+41
* Only depend on Abseil in threaded builds.whitequark2021-03-101-0/+6
* Merge pull request #607 from litghost/add_absl_flat_hash_mapgatecat2021-03-091-1/+2
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| * Add absl::flat_hash_map.Keith Rothman2021-03-011-1/+2
* | Merge pull request #609 from YosysHQ/gatecat/sta-v2gatecat2021-03-098-242/+937
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| * | timing: Integration tweaksgatecat2021-03-054-4/+9
| * | timing: Skip route delays for unplaced/nullptr cellsgatecat2021-03-041-1/+6
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