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path: root/common/nextpnr.h
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* Split nextpnr.h to allow for linear inclusion.Keith Rothman2021-03-151-1508/+5
* Add support for partially routed nets from the placer in router2.Keith Rothman2021-03-121-3/+6
* timing: Add backwards path walkinggatecat2021-03-041-0/+5
* Remove unused advanced timing constraint APIgatecat2021-02-261-86/+0
* Fix compiler warnings introduced by -Wextragatecat2021-02-251-3/+3
* Change CellInfo in getBelPinsForCellPin to be const.Keith Rothman2021-02-231-2/+2
* Refactor some common code to CellInfo methodsgatecat2021-02-231-0/+8
* Replace DelayInfo with DelayPair/DelayQuadgatecat2021-02-191-10/+13
* Add DelayPair and DelayQuad structuresgatecat2021-02-191-0/+35
* Working on standing up initial constraints system.Keith Rothman2021-02-171-0/+2
* Remove isValidBelForCellgatecat2021-02-161-2/+0
* Merge pull request #575 from YosysHQ/gatecat/belpin-2gatecat2021-02-151-1/+11
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| * Start making use of getBelPinsForCellPin APIgatecat2021-02-101-1/+3
| * Add getBelPinsForCellPin to Arch APIgatecat2021-02-101-0/+8
* | Merge pull request #579 from litghost/add_control_for_split_iogatecat2021-02-121-0/+1
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| * | Add control to whether GenericFrontend splits IO ports.Keith Rothman2021-02-111-0/+1
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* | Make BaseArch getDecalGraphics return an empty rangegatecat2021-02-121-1/+1
* | Merge pull request #580 from litghost/add_design_loaded_state_variablegatecat2021-02-121-0/+5
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| * | Add design_loaded state variable.Keith Rothman2021-02-111-0/+5
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* / Add getBelHidden and add some missing "override" statements.Keith Rothman2021-02-111-2/+5
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* Remove the unused CellInfo::pins fieldgatecat2021-02-101-3/+0
* Add BaseArchRanges for default ArchRanges typesgatecat2021-02-091-0/+21
* Make BaseCtx destructor virtualgatecat2021-02-081-1/+1
* Use 'T' postfix to disambiguate LHS and RHS of usingD. Shah2021-02-081-42/+48
* Add archArgs and archArgsToId to Arch APID. Shah2021-02-051-0/+3
* ice40: Switch to BaseArchD. Shah2021-02-051-0/+1
* Add pure-virtual ArchAPI interfaceD. Shah2021-02-051-104/+198
* Rename ArchBase to BaseArch for consistency with BaseCtxD. Shah2021-02-051-1/+1
* Add default implementation of bel bucket functionsD. Shah2021-02-051-5/+89
* Add default implementation of some range-returning functionsD. Shah2021-02-051-5/+27
* Add a few more functions to ArchBaseD. Shah2021-02-051-8/+14
* ecp5: Use common wire/pip bindingD. Shah2021-02-051-1/+1
* Fix now-illegal use of reinterpret_castD. Shah2021-02-051-3/+5
* nextpnr: Example of shared wire/bel/pip binding codeD. Shah2021-02-051-13/+106
* nextpnr: Use templates to specify range typesD. Shah2021-02-051-0/+21
* nextpnr: Add base virtual functions for non-range Arch APID. Shah2021-02-051-0/+108
* Mark IdString and IdStringList single argument constructors explicit.Keith Rothman2021-02-041-4/+5
* generic: Use IdStringList for all arch object namesD. Shah2021-02-021-0/+15
* nexus: Implement IdStringList for all arch object namesD. Shah2021-02-021-0/+6
* ecp5: Implement IdStringList for all arch object namesD. Shah2021-02-021-1/+24
* ecp5: Proof-of-concept using IdStringList for bel namesD. Shah2021-02-021-4/+22
* common: First pass at IdStringList methodsD. Shah2021-02-021-3/+29
* common: Adding IdStringList typeD. Shah2021-02-021-0/+67
* clangformatD. Shah2021-01-281-5/+2
* C++17 compatibility: Don't use std::random_shufflePer Grön2020-12-301-4/+10
* Only print filenames for now, default onRoss Schlaikjer2020-08-301-4/+2
* Add option to print critical path source codeRoss Schlaikjer2020-08-301-0/+5
* Port nextpnr-{ice40,ecp5} to WASI.whitequark2020-05-231-0/+14
* svg: Basic SVG graphics renderingDavid Shah2020-02-151-0/+5
* ecp5: Router2 test integrationDavid Shah2020-02-031-0/+22
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