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* Fix hidpi, fixes #167, fixes #275, fixes #425Miodrag Milanovic2021-05-312-3/+10
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* Merge pull request #714 from YosysHQ/gatecat/mistral-dis-compressgatecat2021-05-302-1/+9
|\ | | | | mistral: Make RBF compression optional
| * mistral: Make RBF compression optionalgatecat2021-05-302-1/+9
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #713 from YosysHQ/gatecat/version-bumpgatecat2021-05-272-1/+1
|\ | | | | interchange: Bump versions
| * interchange: Bump versionsgatecat2021-05-272-1/+1
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #686 from YosysHQ/gatecat/interchange-macrogatecat2021-05-2114-4/+414
|\ | | | | interchange: Add macro expansion
| * interchange: Bump versionsgatecat2021-05-212-1/+1
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * interchange: Add macro parameter mappinggatecat2021-05-212-3/+53
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * interchange: Don't error out on missing cell portsgatecat2021-05-212-2/+3
| | | | | | | | | | | | | | This is required for LUTRAM support, as the upper address bits of RAMD64E etc are missing for shallower primitives. Signed-off-by: gatecat <gatecat@ds0.me>
| * interchange: Add LUTRAM testgatecat2021-05-216-0/+169
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * interchange: Preliminary implementation of macro expansiongatecat2021-05-213-0/+116
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * interchange: Add macro param map rules to chipdbgatecat2021-05-211-0/+24
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * interchange: Add macro data to chipdbgatecat2021-05-211-1/+51
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #712 from YosysHQ/gatecat/rr-heatmapgatecat2021-05-216-3/+64
|\ | | | | router2: Add heatmap by routing resource type
| * router2: Add heatmap by routing resource typegatecat2021-05-206-3/+64
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | Merge pull request #711 from acomodi/interchange-site-to-pseudo-pipsgatecat2021-05-203-4/+29
|\ \ | |/ |/| interchange: phys: add site instance idstr for pseudo tile PIPs
| * gh-actions: interchange: use commit sha as cache keyAlessandro Comodi2021-05-201-4/+10
| | | | | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
| * bump interchange schemaAlessandro Comodi2021-05-201-0/+0
| | | | | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
| * interchange: phys: add site instance idstr for pseudo tile PIPsAlessandro Comodi2021-05-191-0/+19
|/ | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* Run clangformatgatecat2021-05-163-6/+8
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #708 from Ravenslofty/mistral-getchipnamegatecat2021-05-151-1/+1
|\ | | | | mistral: add getChipName
| * mistral: add getChipNameLofty2021-05-151-1/+1
|/ | | | Signed-off-by: Lofty <dan.ravensloft@gmail.com>
* Merge pull request #707 from gatecat/cyclonevgatecat2021-05-1531-9/+4222
|\ | | | | mistral: Initial Cyclone V support
| * Update READMEgatecat2021-05-151-0/+1
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * mistral: Add MISTRAL_CLKBUF cell typegatecat2021-05-155-1/+15
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * ci: Use GH only for Mistral and fpga-interchangegatecat2021-05-153-2/+58
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * mistral: Tidying upgatecat2021-05-1512-12/+13
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * mistral: Make router2 the defaultgatecat2021-05-151-1/+1
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * router2: Hacky workaround for slow Cyclone V convergencegatecat2021-05-151-3/+3
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * mistral: Speed up bel binding and checkinggatecat2021-05-151-4/+18
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * mistral: Workaround for weird SCLR issuegatecat2021-05-151-0/+7
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * mistral: Fix ENA and ACLR bitstream generationgatecat2021-05-154-4/+11
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * mistral: Disable global buffers that are currently brokengatecat2021-05-151-0/+2
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * router2: Reduce verbosity when debugginggatecat2021-05-151-0/+2
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * mistral: Compensate for EF_SEL mirroring in validity checkgatecat2021-05-151-2/+2
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * mistral: Fix EF_SEL and BTO_DISgatecat2021-05-152-4/+5
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * mistral: PKREG bits appear to be mirrored within a half?gatecat2021-05-151-2/+3
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * mistral: Debugging flipflopsgatecat2021-05-151-3/+4
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * mistral: Trim SDATA if SLOAD is lowgatecat2021-05-151-0/+9
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * mistral: FF&CLKBUF fixes, part 1gatecat2021-05-152-1/+10
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * mistral: First pass at FF and CLKBUF bitgengatecat2021-05-152-18/+115
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * mistral: Account for TD input count limitgatecat2021-05-154-9/+128
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * msitral: Fix pip iterator Python bindingsgatecat2021-05-151-2/+2
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * mistral: Implement PIP locations, toogatecat2021-05-151-1/+1
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * mistral: Implement bounding boxes for router2gatecat2021-05-152-1/+15
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * mistral: Debugging carry chain issuesgatecat2021-05-152-13/+34
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * mistral: Adding FF control set reservationgatecat2021-05-153-58/+148
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * mistral: Carry fixesgatecat2021-05-152-3/+16
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * mistral: Carry debugginggatecat2021-05-153-41/+11
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * mistral: Write arith mode to bitstream (not yet functional)gatecat2021-05-152-2/+18
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
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