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| * interchange: pseudo pips: fix illegal tile pseudo PIPsAlessandro Comodi2021-05-143-21/+62
|/ | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* Merge pull request #700 from acomodi/fix-illegal-site-thrugatecat2021-05-133-16/+58
|\ | | | | interchange: arch: do not allow site pips within sites
| * interchange: site router: add valid pips list to check during routingAlessandro Comodi2021-05-133-11/+59
| | | | | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
| * interchange: arch: do not allow site pips within sitesAlessandro Comodi2021-05-121-6/+0
|/ | | | | | | | | | | | During general routing, the only site pips that can be allowed are those which connect a site wire to the routing interface. This might be too restrictive when dealing with architectures that require more than one site PIPs to route from a driver within a site to the routing interface (which is something that should be allowed in the interchange). Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* Merge pull request #704 from YosysHQ/router2_statsgatecat2021-05-121-0/+33
|\ | | | | router2: Add some boundness statistics
| * router2: Add some boundness statisticsgatecat2021-05-121-0/+33
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Update READMEgatecat2021-05-111-1/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #702 from YosysHQ/gatecat/interchange-fix-bbgatecat2021-05-112-3/+3
|\ | | | | interchange: Fix bounding box computation
| * router2: Fix a typogatecat2021-05-111-1/+1
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * interchange: Fix bounding box computationgatecat2021-05-111-2/+2
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #701 from YosysHQ/gatecat/finer-debuggatecat2021-05-111-0/+11
|\ | | | | command: Allow debug output for just placer or router
| * command: Allow debug output for just placer or routergatecat2021-05-111-0/+11
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #695 from acomodi/fix-illegal-site-thrugatecat2021-05-102-2/+25
|\ | | | | interchange: fix site-thru pip legality
| * interchange: site router: fix log messagesAlessandro Comodi2021-05-101-3/+3
| | | | | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
| * interchange: site router: fix illegal site thru pathsAlessandro Comodi2021-05-102-0/+23
|/ | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* Merge pull request #694 from YosysHQ/gatecat/interchange-glbroutegatecat2021-05-075-2/+337
|\ | | | | interchange: Initial global routing implementation
| * interchange: Bump versiongatecat2021-05-071-1/+1
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * interchange: Adding a basic global buffer placergatecat2021-05-073-32/+132
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * interchange: Initial global routing implementationgatecat2021-05-073-0/+222
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * interchange: Add more global cell infogatecat2021-05-071-1/+14
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #697 from YosysHQ/gatecat/router2-dynamic-bb-expandgatecat2021-05-061-23/+61
|\ | | | | router2: Dynamicly expand bounding box based on congestion
| * router2: Reserve wires in more complex casesgatecat2021-05-061-13/+39
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * router2: Dynamicly expand bounding box based on congestiongatecat2021-05-061-10/+22
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Revert "nexus: Enable placeAllAtOnce"gatecat2021-05-061-1/+4
| | | | This reverts commit 0abe425675ae0cc550194171f1f15ec4058a05d6.
* Merge pull request #688 from YosysHQ/gatecat/new-cluster-apigatecat2021-05-0626-391/+411
|\ | | | | New cluster API
| * Add stub cluster API impl for remaining archesgatecat2021-05-067-2/+34
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * nexus: Use new cluster APIgatecat2021-05-063-13/+17
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * base_arch: Fix typo in getClusterPlacementgatecat2021-05-061-1/+1
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * ecp5: Use new cluster APIgatecat2021-05-063-20/+29
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * Update placers to use new cluster APIsgatecat2021-05-0610-346/+151
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * Add default base implementation of cluster APIgatecat2021-05-066-7/+104
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * Add BaseClusterInfo for base implementationgatecat2021-05-061-0/+44
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * arch_api: Outline of new cluster APIgatecat2021-05-064-14/+43
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #692 from davidcorrigan714/patch-1gatecat2021-05-011-2/+2
|\ | | | | Fix variable name in bits.h for MSVC builds
| * Update bits.hDavid Corrigan2021-04-301-2/+2
|/ | | Fixed the variable name for windows MSVC builds.
* clangformatgatecat2021-04-301-40/+30
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #664 from YosysHQ/gatecat/nexus-countergatecat2021-04-308-3/+61
|\ | | | | interchange/nexus: Add counter example
| * interchange/nexus: Add counter examplegatecat2021-04-308-3/+61
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #690 from YosysHQ/gatecat/interchange-wire-typesgatecat2021-04-305-4/+39
|\ | | | | interchange: Add wire types
| * interchange: Bump versionsgatecat2021-04-301-2/+2
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * interchange: Implement getWireTypegatecat2021-04-303-1/+20
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * interchange: Add wire types to chipdbgatecat2021-04-301-1/+17
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #689 from adamgreig/ecp5-alugatecat2021-04-293-1/+140
|\ | | | | ECP5 ALU54B placement support
| * Only set CIBOUT_BYP on MULTs that are not feeding an ALU.Adam Greig2021-04-291-1/+1
| |
| * Add check_alu to Ecp5PackerAdam Greig2021-04-291-15/+123
| | | | | | | | | | | | | | | | | | | | | | Checks that every ALU54B is correctly connected to two MULT18X18Ds: * SIGNEDIA and SIGNEDIB connected to SIGNEDP * MA and MB connected to P * A and B connected to {ROA, ROB} Diamond enforces these requirements; the connections are fixed in any event so no other connection is possible.
| * Add relative constraints to position MULT18X18D near connected ALU54B.Adam Greig2021-04-292-0/+29
| |
| * Add ALU54B.REG_OPCODEOP1_1_CLK parameter supportAdam Greig2021-04-291-0/+2
|/
* Merge pull request #685 from YosysHQ/gatecat/nexus-routinggatecat2021-04-251-4/+1
|\ | | | | nexus: Enable placeAllAtOnce
| * nexus: Enable placeAllAtOncegatecat2021-04-251-4/+1
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #683 from antmicro/interchange-allow-loc-keywordgatecat2021-04-201-2/+4
|\ | | | | interchange: allow LOC keyword in XDC files
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