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* Merge pull request #159 from YosysHQ/ecp5_pllplaceDavid Shah2018-12-012-2/+59
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| * ecp5: Pre-place PLLs and use dedicated routes into globalsDavid Shah2018-11-302-2/+59
* | Merge pull request #158 from YosysHQ/improve_errorDavid Shah2018-11-295-10/+14
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| * ice40: Add a warning for unconstrained IODavid Shah2018-11-291-6/+5
| * rulecheck: Improve message printed at startDavid Shah2018-11-291-1/+1
| * Improve reporting of unknown cell typesDavid Shah2018-11-292-2/+3
| * json: Improve reporting of multiple driversDavid Shah2018-11-291-1/+5
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* Merge pull request #157 from whitequark/fanout-threshDavid Shah2018-11-291-1/+1
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| * ice40: raise CE global promotion threshold.whitequark2018-11-291-1/+1
* | Merge pull request #156 from whitequark/fanoutDavid Shah2018-11-291-7/+11
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| * ice40: print fanout of nets promoted to globals.whitequark2018-11-281-7/+11
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* Merge pull request #155 from smunaut/issue_151David Shah2018-11-281-48/+48
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| * ice40: Update the way LVDS inputs are handled during bitstream generationSylvain Munaut2018-11-281-48/+48
* | Merge pull request #154 from smunaut/issue_141David Shah2018-11-281-72/+212
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| * ice40: Try to be helpful and suggest using PAD PLL instead of CORESylvain Munaut2018-11-281-2/+14
| * ice40: Revamp the whole PLL placement/validity check logicSylvain Munaut2018-11-281-72/+200
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* Merge pull request #153 from YosysHQ/global-optionsDavid Shah2018-11-282-3/+14
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| * ice40: Finer-grained control of global promotionDavid Shah2018-11-272-3/+14
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* Merge pull request #152 from YosysHQ/compile_fixDavid Shah2018-11-271-0/+10
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| * Fix compile on GCC 5.5 or olderMiodrag Milanovic2018-11-271-0/+10
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* Merge pull request #150 from YosysHQ/err_warn_countDavid Shah2018-11-264-2/+19
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| * Print warning and error count at end of executionDavid Shah2018-11-264-2/+19
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* timing: Improve clock constraint log outputDavid Shah2018-11-261-2/+6
* Merge pull request #149 from smunaut/issue_148David Shah2018-11-264-10/+43
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| * ice40: During global promotion, only promote if this will actually fit !Sylvain Munaut2018-11-261-6/+32
| * ice40: Add helper to know which global network is driven by a SB_GB BelSylvain Munaut2018-11-262-2/+8
| * placer1: During initial placement, don't rip-up strongly binded cellsSylvain Munaut2018-11-261-2/+3
* | ecp5: Fix UR PLL tile coordinatesDavid Shah2018-11-261-2/+2
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* Update README.mdDavid Shah2018-11-261-4/+6
* clangformatDavid Shah2018-11-261-1/+1
* Merge pull request #143 from daveshah1/ecp5_muxesDavid Shah2018-11-265-6/+169
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| * ecp5: Add support for LUT7 muxDavid Shah2018-11-181-6/+116
| * ecp5: More optimal LUT6 placementDavid Shah2018-11-163-1/+11
| * ecp5: Adding mux support up to LUT6David Shah2018-11-163-6/+49
* | Merge pull request #138 from YosysHQ/refactor_logDavid Shah2018-11-268-123/+84
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| * | Add nonfatal error support and use for timing failuresDavid Shah2018-11-264-3/+14
| * | Change the log level of some timing-related messagesDavid Shah2018-11-213-16/+20
| * | Refactor log code and add log file supportDavid Shah2018-11-215-106/+52
* | | Merge pull request #139 from YosysHQ/fix_117David Shah2018-11-261-1/+6
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| * | | router1: Fix unrouted, undriven netsDavid Shah2018-11-211-1/+6
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* | | json: Remove superfluous floating node messageDavid Shah2018-11-261-5/+0
* | | ice40: Improve PCF error handlingDavid Shah2018-11-261-3/+9
* | | Merge branch 'master' of github.com:YosysHQ/nextpnrDavid Shah2018-11-262-1/+3
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| * \ \ Merge pull request #146 from YosysHQ/fix_145David Shah2018-11-241-0/+2
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| | * | | ice40: Fix disconnection of PACKAGEPIN for PAD PLLsDavid Shah2018-11-241-0/+2
| * | | | Merge pull request #144 from bgamari/patch-1David Shah2018-11-221-1/+1
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| | * | | docs/constraints: Fix typoBen Gamari2018-11-221-1/+1
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* / / / python: Fixes to get net wires map workingDavid Shah2018-11-223-4/+55
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* | | python: Add wrapper for vectors to allow Python access to net.usersDavid Shah2018-11-223-4/+76
* | | Merge pull request #122 from YosysHQ/ecp5_timingDavid Shah2018-11-229-134/+372
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