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* added siologicMiodrag Milanovic2019-12-134-2/+63
* Add many new wiresMiodrag Milanovic2019-12-134-0/+1250
* clangformat runMiodrag Milanovic2019-12-084-330/+365
* display IOs properlyMiodrag Milanovic2019-12-071-21/+5
* More bels show properlyMiodrag Milanovic2019-12-071-43/+82
* add dcca bels and dummy parts for other belsMiodrag Milanovic2019-12-071-9/+54
* Fix edge wiresMiodrag Milanovic2019-12-071-69/+108
* add more pipsMiodrag Milanovic2019-12-011-0/+49
* Handle H00 and V00Miodrag Milanovic2019-11-111-6/+49
* More pips and fix for V01Miodrag Milanovic2019-11-111-42/+170
* cleanupMiodrag Milanovic2019-11-111-174/+78
* proper h06 and v06Miodrag Milanovic2019-11-111-34/+39
* More pips addedMiodrag Milanovic2019-11-101-41/+200
* more pips, and valid mappingMiodrag Milanovic2019-11-102-10/+23
* Fixed V2, some more pipsMiodrag Milanovic2019-11-101-12/+43
* more pipsMiodrag Milanovic2019-11-101-2/+43
* Draw some pips, fixed H6 and V6Miodrag Milanovic2019-11-093-31/+58
* Show V02/V06/H02/H06Miodrag Milanovic2019-10-253-13/+105
* display horizontal wires, add some globals to listMiodrag Milanovic2019-10-234-1/+123
* Split graphics calls for wires into gfx.ccMiodrag Milanovic2019-10-203-268/+304
* type needs to be part of hash for GroupIdMiodrag Milanovic2019-10-201-1/+3
* muxes only together with slicesMiodrag Milanovic2019-10-201-9/+7
* Remove not used lineMiodrag Milanovic2019-10-201-2/+0
* Simplify layout of elementsMiodrag Milanovic2019-10-204-400/+254
* fix slice wireMiodrag Milanovic2019-10-201-20/+20
* bound signalsMiodrag Milanovic2019-10-201-0/+65
* more wires between switchboxesMiodrag Milanovic2019-10-204-2/+59
* Add more types of wiresMiodrag Milanovic2019-10-202-177/+221
* Less types neededMiodrag Milanovic2019-10-202-56/+24
* finixed slice wiresMiodrag Milanovic2019-10-201-0/+27
* wd wiresMiodrag Milanovic2019-10-202-1/+32
* Fix look of some wiresMiodrag Milanovic2019-10-201-6/+9
* Add output wiresMiodrag Milanovic2019-10-201-0/+35
* fix mux displayMiodrag Milanovic2019-10-201-2/+2
* set wire active flagMiodrag Milanovic2019-10-202-1/+3
* clk and lsr muxesMiodrag Milanovic2019-10-202-1/+93
* draw rest of slice wires and more from switchboxMiodrag Milanovic2019-10-202-7/+106
* OptimizeMiodrag Milanovic2019-10-202-18/+87
* Add other side of slice wiresMiodrag Milanovic2019-10-202-14/+118
* Display rest of slice input wiresMiodrag Milanovic2019-10-202-3/+69
* Add more zoomMiodrag Milanovic2019-10-201-1/+1
* Start adding visible wiresMiodrag Milanovic2019-10-205-10/+99
* Added type to wireMiodrag Milanovic2019-10-203-1/+87
* Draw swbox, smaller slices, proper ioMiodrag Milanovic2019-10-204-28/+157
* Merge pull request #342 from xobs/msvc-static-fixDavid Shah2019-10-181-1/+1
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| * cmake: don't link libutil on windowsSean Cross2019-10-181-1/+1
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* Merge pull request #341 from YosysHQ/dave/ice40-pcf-frequencyDavid Shah2019-10-132-0/+21
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| * ice40: Add set_frequency pcf command; and document pcfDavid Shah2019-10-132-0/+21
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* Merge pull request #340 from YosysHQ/dave/ecp5_ioDavid Shah2019-10-135-9/+217
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| * ecp5: Add support for ECLKBRIDGECSDavid Shah2019-10-111-1/+52