added siologic

4 files changed, 63 insertions, 2 deletions

diff --git a/ecp5/constids.inc b/ecp5/constids.inc
index 9170f225..656dd1b7 100644
--- a/ecp5/constids.inc
+++ b/ecp5/constids.inc
@@ -1299,6 +1299,7 @@ X(WIRE_TYPE_NONE)
 X(WIRE_TYPE_SLICE)
 X(WIRE_TYPE_DQS)
 X(WIRE_TYPE_IOLOGIC)
+X(WIRE_TYPE_SIOLOGIC)
 X(WIRE_TYPE_PIO)
 X(WIRE_TYPE_DDRDLL)
 X(WIRE_TYPE_EBR)
diff --git a/ecp5/gfx.cc b/ecp5/gfx.cc
index 3d37e2a9..188e44ab 100644
--- a/ecp5/gfx.cc
+++ b/ecp5/gfx.cc
@@ -112,8 +112,24 @@ void gfxTileWire(std::vector<GraphicElement> &g, int x, int y, int w, int h, IdS
         el.y1 = y + io_cell_v_y1 + gap * 0.10 + 0.0017f * (num + 1);
         el.y2 = el.y1;
         g.push_back(el);
-    }    
-
+    }
+    if (wire_type == id_WIRE_TYPE_SIOLOGIC) {
+        GraphicElement el;
+        el.type = GraphicElement::TYPE_LINE;
+        el.style = style;
+        int gap = (tilewire - TILE_WIRE_JLOADNB_SIOLOGIC)/20;
+        int num = (tilewire - TILE_WIRE_JLOADNB_SIOLOGIC)%20;
+        el.x1 = x + io_cell_h_x1 + (5-gap) * 0.10 + 0.0017f * (num + 1);
+        el.x2 = el.x1;
+        if (y == h - 1) {
+            el.y1 = y + 1 - io_cell_h_y2;
+            el.y2 = el.y1 - 0.015f;
+        } else {
+            el.y1 = y + io_cell_h_y2;
+            el.y2 = el.y1 + 0.015f;
+        }
+        g.push_back(el);
+    }
     if (wire_type == id_WIRE_TYPE_DQS) {
         GraphicElement el;
         el.type = GraphicElement::TYPE_LINE;
diff --git a/ecp5/gfx.h b/ecp5/gfx.h
index 4c9b926f..2dda3301 100644
--- a/ecp5/gfx.h
+++ b/ecp5/gfx.h
@@ -636,6 +636,47 @@ enum GfxTileWireId
     TILE_WIRE_WRPNTR1A_IOLOGIC,
     TILE_WIRE_WRPNTR2A_IOLOGIC,
 
+    TILE_WIRE_JLOADNB_SIOLOGIC,
+    TILE_WIRE_JMOVEB_SIOLOGIC,
+    TILE_WIRE_JDIRECTIONB_SIOLOGIC,
+    TILE_WIRE_JCFLAGB_SIOLOGIC,
+    TILE_WIRE_IOLDOB_SIOLOGIC,
+    TILE_WIRE_IOLTOB_SIOLOGIC,
+    TILE_WIRE_DIB_SIOLOGIC,
+    TILE_WIRE_IOLDODB_SIOLOGIC,
+    TILE_WIRE_IOLDOIB_SIOLOGIC,
+    TILE_WIRE_INDDB_SIOLOGIC,
+    TILE_WIRE_PADDIB_SIOLOGIC,
+    TILE_WIRE_JCLKB_SIOLOGIC,
+    TILE_WIRE_JCEB_SIOLOGIC,
+    TILE_WIRE_JLSRB_SIOLOGIC,
+    TILE_WIRE_JTSDATA0B_SIOLOGIC,
+    TILE_WIRE_JTXDATA0B_SIOLOGIC,
+    TILE_WIRE_JTXDATA1B_SIOLOGIC,
+    TILE_WIRE_JRXDATA0B_SIOLOGIC,
+    TILE_WIRE_JRXDATA1B_SIOLOGIC,
+    TILE_WIRE_JINFFB_SIOLOGIC,
+    TILE_WIRE_JLOADNA_SIOLOGIC,
+    TILE_WIRE_JMOVEA_SIOLOGIC,
+    TILE_WIRE_JDIRECTIONA_SIOLOGIC,
+    TILE_WIRE_JCFLAGA_SIOLOGIC,
+    TILE_WIRE_IOLDOA_SIOLOGIC,
+    TILE_WIRE_IOLTOA_SIOLOGIC,
+    TILE_WIRE_DIA_SIOLOGIC,
+    TILE_WIRE_IOLDODA_SIOLOGIC,
+    TILE_WIRE_IOLDOIA_SIOLOGIC,
+    TILE_WIRE_INDDA_SIOLOGIC,
+    TILE_WIRE_PADDIA_SIOLOGIC,
+    TILE_WIRE_JCLKA_SIOLOGIC,
+    TILE_WIRE_JCEA_SIOLOGIC,
+    TILE_WIRE_JLSRA_SIOLOGIC,
+    TILE_WIRE_JTSDATA0A_SIOLOGIC,
+    TILE_WIRE_JTXDATA0A_SIOLOGIC,
+    TILE_WIRE_JTXDATA1A_SIOLOGIC,
+    TILE_WIRE_JRXDATA0A_SIOLOGIC,
+    TILE_WIRE_JRXDATA1A_SIOLOGIC,
+    TILE_WIRE_JINFFA_SIOLOGIC,
+
     TILE_WIRE_PADDOD_PIO,
     TILE_WIRE_PADDTD_PIO,
     TILE_WIRE_JPADDID_PIO,
diff --git a/ecp5/trellis_import.py b/ecp5/trellis_import.py
index edafebfa..0ae8dde5 100755
--- a/ecp5/trellis_import.py
+++ b/ecp5/trellis_import.py
@@ -56,6 +56,9 @@ def wire_type(name):
     if name[0].endswith("_IOLOGIC"):
         return "WIRE_TYPE_IOLOGIC"
 
+    if name[0].endswith("_SIOLOGIC"):
+        return "WIRE_TYPE_SIOLOGIC"
+
     if name[0].endswith("_PIO"):
         return "WIRE_TYPE_PIO"