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* [interchange] Disallow site edges during general routing.Keith Rothman2021-04-062-5/+23
| | | | | | | This prevents the general router from routing through sites, which is not legal in FPGA interchange. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* [interchange] Add crude pseudo pip model.Keith Rothman2021-04-066-7/+717
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Fix bug in router2 where router may give up too early.Keith Rothman2021-04-061-1/+13
| | | | | | | | | | Was introduced in #612. The logic before was intended to prevent the router from terminating early when not using a bounding box, but the fix in #612 simply removed that, meaning that the router might terminate early incorrectly. The solution here is to only use the toexplore hysteric once a solution is found. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Merge pull request #661 from litghost/document_site_routergatecat2021-04-061-10/+58
|\ | | | | [interchange] Add some documentation for the site router.
| * [interchange] Add some documentation for the site router.Keith Rothman2021-04-051-10/+58
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* | Merge pull request #662 from litghost/fix_cirrus_cigatecat2021-04-061-1/+1
|\ \ | | | | | | Increase vCPU to 5 because of cirrus resource limit change.
| * | Increase vCPU to 5 because of cirrus resource limit change.Keith Rothman2021-04-051-1/+1
| |/ | | | | | | | | | | Cirrus CI now requires that RAM (in GiB) be less than 4*vCPU. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* | Merge pull request #657 from acomodi/interchange-counter-multi-boardgatecat2021-04-065-23/+25
|\ \ | |/ |/| interchange: counter: testing on multiple boards
| * interchange: counter: testing on multiple boardsAlessandro Comodi2021-04-015-23/+25
| | | | | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* | Merge pull request #658 from litghost/increment_chipdbgatecat2021-04-025-5/+14
|\ \ | |/ |/| [interchange] Update to v6 of FPGA interchange chipdb.
| * [interchange] Update interchange CI for new chipdb change.Keith Rothman2021-04-012-3/+2
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * [interchange] Update to v6 of FPGA interchange chipdb.Keith Rothman2021-04-013-2/+12
|/ | | | | | | Changes: - Adds LUT output pin to LutBelPOD. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Merge pull request #646 from YosysHQ/gatecat/nexus-cmakegatecat2021-03-3115-133/+385
|\ | | | | fpga_interchange: Add CMake support for Nexus/prjoxide
| * interchange: Fix nexus cmake review commentsgatecat2021-03-314-16/+11
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * ci: Build prjoxide only for LIFCLgatecat2021-03-302-7/+8
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * interchange: Split xc7 and nexus chipdb cmakegatecat2021-03-303-243/+245
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * interchange: Add Nexus LUT testgatecat2021-03-308-20/+140
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * interchange: Add Nexus to CIgatecat2021-03-305-2/+21
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * interchange: Add CMake support for Nexus/prjoxidegatecat2021-03-303-0/+115
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | Merge pull request #656 from litghost/fix_dedicated_interconnect_buggatecat2021-03-302-10/+23
|\ \ | | | | | | Fix bug where DedicateInterconnect incorrectly allows some placements.
| * | Fix bug where DedicateInterconnect incorrectly allows some placement.Keith Rothman2021-03-302-10/+23
|/ / | | | | | | | | | | | | This occurs when the driver pin and sink pin are part of the same site, but not reachable with site routing only. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* | Merge pull request #653 from litghost/fix_site_pip_checkgatecat2021-03-301-7/+22
|\ \ | |/ |/| [interchange] Fix site pip check for drivers.
| * [interchange] Fix site pip check for drivers.Keith Rothman2021-03-301-7/+22
|/ | | | | | Previous code allowed router to entire sites with no sinks. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Merge pull request #655 from YosysHQ/gatecat/alt-placer-fixgatecat2021-03-302-7/+8
|\ | | | | interchange: Fix illegal placements
| * interchange: Fix illegal placementsgatecat2021-03-302-7/+8
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* nexus: Fix some IO FASM gengatecat2021-03-301-0/+4
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* nexus: Fix LIFCL-17 LRAM FASMgatecat2021-03-301-0/+2
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* nexus: Fix default IO configgatecat2021-03-291-0/+2
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #651 from YosysHQ/gatecat/nexus-vccogatecat2021-03-291-3/+51
|\ | | | | nexus: Fix bank Vcco FASM
| * nexus: Fix bank Vcco FASMgatecat2021-03-291-3/+51
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | nexus: Default HF_OSC_EN to ENABLEDgatecat2021-03-291-1/+1
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #645 from litghost/add_counter_and_ramgatecat2021-03-2923-337/+1221
|\ | | | | FPGA interchange: Add counter and ram tests
| * Update README with latest develpment progress.Keith Rothman2021-03-252-146/+39
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * interchange: Fix bug in site router where a bad solution isn't remove.Keith Rothman2021-03-251-3/+7
| | | | | | | | | | | | | | This resulted in valid site routing solutions being missed. Underlying bug was an off-by-one error when unwinding a failed solution. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * Implement debugging tools for site router.Keith Rothman2021-03-257-23/+166
| | | | | | | | | | | | | | | | - Finishes implementation of SiteArch::nameOfPip and SiteArch::nameOfWire - Adds "explain_bel_status", which should be an exhaustive diagnostic of the status of a BEL placement. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * Add some FIXME's around VCC assumption in LUT logic.Keith Rothman2021-03-251-0/+17
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * Add targets to generate YAML outputs for DeviceResource files.Keith Rothman2021-03-251-0/+22
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * Re-work LUT mapping logic to only put VCC pins when required.Keith Rothman2021-03-255-104/+174
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * Fixup some of the re-mapping logic.Keith Rothman2021-03-252-27/+75
| | | | | | | | | | | | | | - Add IDEMPOTENT_CHECK define to perform some expected idempotent operations more than once to verify they work as expected. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * Add initial handling of local site inverters and constant signals.Keith Rothman2021-03-258-60/+460
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * [FPGA interchange] Small fix to get_net_type.Keith Rothman2021-03-252-9/+14
| | | | | | | | | | | | | | If get_net_type was called before the driver was placed, it could return the wrong value. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * Enable counter tests and add RAM tests.Keith Rothman2021-03-256-2/+284
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* | Merge pull request #649 from acomodi/add-archcheck-to-all-testsgatecat2021-03-263-9/+41
|\ \ | | | | | | interchange: add archcheck tests to all-device-test target
| * | gh-actions: better yosys caching based on versionAlessandro Comodi2021-03-262-6/+35
| | | | | | | | | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
| * | interchange: add archcheck tests to all-device-test targetAlessandro Comodi2021-03-262-3/+6
|/ / | | | | | | | | | | | | This increases parallelism and should make the FPGA interchange CI faster Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* | Merge pull request #650 from YosysHQ/gatecat/nexus-17k-fixesgatecat2021-03-261-1/+4
|\ \ | |/ |/| nexus: Fix FASM gen for LIFCL-17
| * nexus: Fix FASM gen for LIFCL-17gatecat2021-03-261-1/+4
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #648 from YosysHQ/gatecat/nexus-get_pinsgatecat2021-03-251-7/+56
|\ | | | | nexus: Add support for get_pins PDC command
| * nexus: Add support for get_pins PDC commandgatecat2021-03-251-7/+56
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #628 from acomodi/add-interchange-devicesgatecat2021-03-2522-168/+450
|\ | | | | fpga_interchange: add more devices
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-03 08:48:47 +0000