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| * Added tying unused LUT pins to preferred constant instead of VccMaciej Kurc2022-05-111-2/+8
| * Generalized representation of unused LUT pins connectionsMaciej Kurc2022-05-115-58/+160
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* Merge pull request #984 from yrabbit/assertmyrtle2022-05-101-1/+1
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| * common: Correct a minor typo in the messageYRabbit2022-05-101-1/+1
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* Merge pull request #982 from YosysHQ/gatecat/ice40-gb-constr-fixmyrtle2022-05-081-7/+24
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| * ice40: Fix propagation of constraints through SB_GBgatecat2022-05-081-7/+24
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* Merge pull request #981 from yrabbit/lw-cst-0gatecat2022-05-031-7/+27
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| * gowin: Add initial syntax support for long wiresYRabbit2022-05-021-7/+27
* | generic: Add some extra helpers for viaduct uarchesgatecat2022-05-024-4/+52
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* generic: Add missing uarch guardgatecat2022-04-271-1/+2
* ecp5: Tweak delay predictiongatecat2022-04-201-1/+1
* Merge pull request #977 from YosysHQ/gatecat/prefine-tileswapgatecat2022-04-192-1/+100
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| * prefine: Do full-tile swaps, toogatecat2022-04-192-1/+100
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* Merge pull request #976 from YosysHQ/gatecat/dp-reworkgatecat2022-04-175-545/+730
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| * Move general parallel detail place code out of parallel_refinegatecat2022-04-175-545/+730
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* Merge pull request #975 from YosysHQ/gatecat/ice40-carry-i3-fixgatecat2022-04-121-34/+45
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| * ice40: Avoid chain finder from mixing up chains by only allowing I3 chaining ...gatecat2022-04-111-34/+45
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* Merge pull request #974 from YosysHQ/gatecat/ci-restructuregatecat2022-04-0816-125/+301
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| * ci: Restructure and move entirely to GH actions from Cirrusgatecat2022-04-0816-125/+301
* | Merge pull request #973 from YosysHQ/gatecat/folder-tidygatecat2022-04-0875-3/+6
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| * Split up common into kernel,place,routegatecat2022-04-0875-3/+6
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* Merge pull request #972 from YosysHQ/gatecat/ecp5-split-slice-v2gatecat2022-04-0713-1349/+1137
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| * ecp5: Split the SLICE bel into separate LUT/FF/RAMW belsgatecat2022-04-0713-1349/+1137
* | Merge pull request #971 from modwizcode/fix-tbb-macosgatecat2022-04-061-1/+1
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| * cmake: properly include TBB libraries.Irides2022-04-051-1/+1
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* generic: Allow bel pins without wiresgatecat2022-04-041-3/+6
* Merge pull request #970 from yrabbit/nr9-wipgatecat2022-04-034-2/+40
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| * gowin: handle the GW1N-9 feature.YRabbit2022-04-034-2/+40
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* clangformatgatecat2022-03-313-12/+12
* Merge pull request #969 from YosysHQ/gatecat/ice40-wirename-fixgatecat2022-03-311-1/+1
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| * ice40: Fix wirenames containing / which is the list separatorgatecat2022-03-301-1/+1
* | Merge pull request #968 from tpambor/gowin-osc-fixgatecat2022-03-302-5/+6
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| * gowin: Fix z-index of oscillatorTim Pambor2022-03-302-5/+6
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* Merge pull request #952 from antmicro/mdudek/nexus_pllgatecat2022-03-303-27/+177
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| * Rename parse_lattice_param to parse_lattice_param_from_cellMaciej Dudek2022-03-303-36/+46
| * Nexus: Fixed OSCA parameters, add pll default parametersMaciej Dudek2022-03-181-2/+142
* | Merge pull request #966 from YosysHQ/gatecat/ice40-optgatecat2022-03-294-4/+91
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| * | ice40: Merge driving LUT<=2s into carry-only LCsgatecat2022-03-294-4/+91
* | | Merge pull request #960 from YosysHQ/gatecat/viaduct-docsgatecat2022-03-292-2/+137
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| * | | docs: Initial reference for the Viaduct 'uarch' APIgatecat2022-03-212-2/+137
* | | | Merge pull request #965 from tpambor/gowin-oscgatecat2022-03-292-0/+46
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| * | | gowin: Add bels for oscillatorTim Pambor2022-03-272-0/+46
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* | | Merge pull request #963 from yrabbit/oddr-quirkgatecat2022-03-264-0/+27
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| * | | gowin: Consider the peculiarity of GW1BR-9CYRabbit2022-03-264-0/+27
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* | | Merge pull request #961 from YosysHQ/ice40/pll-debuggatecat2022-03-251-7/+32
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| * | | ice40: Improve error reporting for PLL conflictsgatecat2022-03-251-7/+32
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* | | gowin: Name the constants (#958)YRabbit2022-03-211-2/+2
* | | Gowin: use global VCC and VSS nets (#956)Pepijn de Vos2022-03-194-10/+22
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* | parallel_refine: Fix compile error with some configsgatecat2022-03-191-1/+1
* | Merge pull request #955 from YosysHQ/gatecat/mistral-updates-2gatecat2022-03-182-2/+2
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