| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| | * | | Move pthread yield hack into BaseCtx | Sergiusz Bazanski | 2018-07-20 | 3 | -10/+14 | |
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| | * | | Mix-in Deterministic RNG at Context instead of BaseCtx | Sergiusz Bazanski | 2018-07-20 | 1 | -2/+2 | |
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| | * | | Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnr into ↵ | Sergiusz Bazanski | 2018-07-20 | 48 | -825/+754 | |
| | |\ \ | | | | | | | | | | | | | q3k/lock-2-electric-boogaloo | |||||
| | * | | | Refactor renderer thread | Sergiusz Bazanski | 2018-07-20 | 2 | -27/+64 | |
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| | * | | | WIP. | Serge Bazanski | 2018-07-17 | 7 | -96/+227 | |
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| | * | | | Add basic external locking, lock from P&R | Serge Bazanski | 2018-07-17 | 3 | -0/+40 | |
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| | * | | | Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnr into ↵ | Serge Bazanski | 2018-07-17 | 25 | -395/+1211 | |
| | |\ \ \ | | | | | | | | | | | | | | | | q3k/lock-2-electric-boogaloo | |||||
| | * \ \ \ | Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnr into ↵ | Serge Bazanski | 2018-07-15 | 16 | -313/+810 | |
| | |\ \ \ \ | | | | | | | | | | | | | | | | | | | q3k/lock-2-electric-boogaloo | |||||
| | * | | | | | Refactor RNG out to separate DeterministicRNG class | Serge Bazanski | 2018-07-14 | 1 | -57/+67 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This well also allow for better lifecycle control over the state of the RNG in the future. | |||||
| | * | | | | | Refactor IdString functionality into IdStringDB | Serge Bazanski | 2018-07-14 | 5 | -27/+33 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This lets us more precisely control the lifetime of IdString databases in contexts/arches. | |||||
| * | | | | | | Add Loc constructors | Clifford Wolf | 2018-07-21 | 4 | -17/+10 | |
| | |_|_|_|/ |/| | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | | | Added driver and users for nets | Miodrag Milanovic | 2018-07-21 | 1 | -0/+8 | |
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| * | | | | | Merge branch 'router1ng' into 'master' | Clifford Wolf | 2018-07-21 | 2 | -87/+341 | |
| |\ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | Router1ng See merge request SymbioticEDA/nextpnr!13 | |||||
| | * | | | | | Bugfix in router1: Also bind src_wire | Clifford Wolf | 2018-07-21 | 1 | -0/+2 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | | | | | Add final sanity check in router1 | Clifford Wolf | 2018-07-21 | 1 | -0/+19 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | | | | | Refactoring of router1 | Clifford Wolf | 2018-07-21 | 2 | -87/+320 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Use source-sink pairs as jobs, not whole nets - Route nets with smallest slack first - Preserve routes for already routed source-sink pairs - Add small incentive for re-using wires Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | | | | Map ports to nets | Miodrag Milanovic | 2018-07-21 | 1 | -0/+14 | |
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| * | | | | | | create io cells out of asc | Miodrag Milanovic | 2018-07-21 | 1 | -0/+27 | |
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| * | | | | | | add cells that are in default state or no configuration | Miodrag Milanovic | 2018-07-21 | 1 | -0/+40 | |
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| * | | | | | | Add used cells and attach them to bels | Miodrag Milanovic | 2018-07-21 | 1 | -0/+39 | |
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| * | | | | | | Fix placement bug with VexRiscV reported by John McMaster | David Shah | 2018-07-21 | 1 | -2/+3 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com> | |||||
| * | | | | | | Assign proper pips | Miodrag Milanovic | 2018-07-21 | 1 | -9/+27 | |
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| * | | | | | | add only missing net | Miodrag Milanovic | 2018-07-21 | 1 | -3/+6 | |
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| * | | | | | Fix minor issue in GUI Wire properties | Clifford Wolf | 2018-07-21 | 1 | -2/+2 | |
| | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | | | Change DelayInfo semantics to what we actually need | Clifford Wolf | 2018-07-21 | 5 | -16/+38 | |
| | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | | | Add getWireDelay API | Clifford Wolf | 2018-07-21 | 4 | -2/+17 | |
| | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | | | Fix warnings and status | Miodrag Milanovic | 2018-07-21 | 3 | -4/+21 | |
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| * | | | | | Made save project work as well | Miodrag Milanovic | 2018-07-21 | 5 | -11/+46 | |
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| * | | | | | made open project to work | Miodrag Milanovic | 2018-07-21 | 1 | -2/+73 | |
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| * | | | | | fix introduced bug | Miodrag Milanovic | 2018-07-21 | 1 | -0/+2 | |
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| * | | | | | make new context work again | Miodrag Milanovic | 2018-07-20 | 1 | -0/+3 | |
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| * | | | | | Bind wires to net | Miodrag Milanovic | 2018-07-20 | 1 | -629/+637 | |
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| * | | | | | Merge branch 'gridapi' into 'master' | David Shah | 2018-07-20 | 6 | -17/+115 | |
| |\ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | Gridapi See merge request SymbioticEDA/nextpnr!11 | |||||
| | * | | | | | Add Location APIs to generic arch | Clifford Wolf | 2018-07-20 | 5 | -24/+49 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | | | | | Improve iCE40 and common Loc code | Clifford Wolf | 2018-07-20 | 4 | -15/+52 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | | | | | Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnr into gridapi | Clifford Wolf | 2018-07-20 | 50 | -872/+911 | |
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| * | | | | | | Few more checks on parameters and error eol | Miodrag Milanovic | 2018-07-20 | 2 | -7/+17 | |
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| * | | | | | | Start adding bitstream reading for ice40 | Miodrag Milanovic | 2018-07-20 | 4 | -43/+143 | |
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| * | | | | | ice40: Optimise reset/enable net checking | David Shah | 2018-07-20 | 3 | -11/+14 | |
| | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com> | |||||
| * | | | | | ice40: Trim DSP inputs that are constant where appropriate | David Shah | 2018-07-19 | 2 | -2/+10 | |
| | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com> | |||||
| * | | | | | ice40: Packer and bitstream gen support for MAC16s | David Shah | 2018-07-19 | 3 | -3/+111 | |
| | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com> | |||||
| * | | | | | ice40: Adding cell definition for DSPs | David Shah | 2018-07-19 | 5 | -7/+80 | |
| | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com> | |||||
| * | | | | | ice40: Add virtual padin wires for intoscs and GB_IOs | David Shah | 2018-07-19 | 1 | -1/+14 | |
| | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com> | |||||
| * | | | | | Reducing performance cost of asserts | David Shah | 2018-07-19 | 2 | -9/+11 | |
| | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com> | |||||
| * | | | | | ice40: Adding data for extra cell configuration | David Shah | 2018-07-19 | 2 | -4/+39 | |
| | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com> | |||||
| * | | | | | Fix click on wire in net section | Miodrag Milanovic | 2018-07-18 | 1 | -1/+1 | |
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| * | | | | | cell and net now can be selected, fixed issue with highlight | Miodrag Milanovic | 2018-07-18 | 1 | -19/+15 | |
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| * | | | | | added clear action for browsing history | Miodrag Milanovic | 2018-07-18 | 4 | -0/+18 | |
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| * | | | | | removed not used and buggy features | Miodrag Milanovic | 2018-07-18 | 13 | -474/+0 | |
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| * | | | | | ecp5: Tidying up examples | David Shah | 2018-07-18 | 10 | -265/+40 | |
| | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com> | |||||
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index : iCE40/nextpnr | |
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