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* always assign budget before placingMiodrag Milanovic2018-07-231-2/+2
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* Add Context::archcheck() and "nextpnr-ice40 --test"Clifford Wolf2018-07-235-45/+208
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Remove getBelsByType() APIClifford Wolf2018-07-234-40/+0
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* clangformatDavid Shah2018-07-232-4/+5
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* ecp5: Add Add getGridDimX(), getGridDimY(), getTileDimZ()David Shah2018-07-231-0/+5
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* clangformatClifford Wolf2018-07-232-20/+26
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add fallback to estimateDelay() in getNetinfoRouteDelay()Clifford Wolf2018-07-231-1/+6
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add getGridDimX(), getGridDimY(), getTileDimZ() APIClifford Wolf2018-07-233-1/+31
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* ecp5: Implement new Grid APIsDavid Shah2018-07-232-0/+50
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* ecp5: Remove obsolete db entries, add Bel z-positionDavid Shah2018-07-232-19/+2
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* Bugfix in iCE40 chipdb.pyClifford Wolf2018-07-231-3/+0
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Added Bel port info to GUIMiodrag Milanovic2018-07-221-0/+8
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* Move to new API and remove deprecatedMiodrag Milanovic2018-07-226-94/+40
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* Move to new apiMiodrag Milanovic2018-07-221-12/+3
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* ecp5: Adding new Bel pin APIDavid Shah2018-07-223-3/+63
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* ecp5: Fix regression following router updateDavid Shah2018-07-222-2/+2
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* Add Arch::getBelPins() to generic and iCE40 archsClifford Wolf2018-07-224-0/+25
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add Arch::getBelPinType() and Arch::getWireBelPins() in iCE40 archClifford Wolf2018-07-223-4/+57
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add Arch::getBelPinType() and Arch::getWireBelPins() in generic archClifford Wolf2018-07-222-2/+12
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Rename getWireBelPin to getBelPinWireClifford Wolf2018-07-2212-26/+26
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Move common patterns from router1 to Context APIClifford Wolf2018-07-223-150/+124
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* clangformatClifford Wolf2018-07-225-39/+30
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* QTimer::start(std::chrono::duration -> int)Sergiusz Bazanski2018-07-212-3/+3
| | | | The chrono::duration-friendly method is availble from Qt 5.8 only.
* Merge branch 'q3k/lock-2-electric-boogaloo' into 'master'Clifford Wolf2018-07-217-161/+397
|\ | | | | | | | | Basic locking and threading for Arch/GUI See merge request SymbioticEDA/nextpnr!10
| * Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnr into ↵Sergiusz Bazanski2018-07-2122-682/+1466
| |\ | | | | | | | | | q3k/lock-2-electric-boogaloo
| * | Re-enable drawing Pips.Sergiusz Bazanski2018-07-201-3/+3
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| * | Use UI lock for yieldingSergiusz Bazanski2018-07-204-14/+40
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| * | clang-formatSergiusz Bazanski2018-07-201-1/+1
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| * | Nuke IdStringDBSergiusz Bazanski2018-07-205-50/+41
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| * | Remove dead code.Sergiusz Bazanski2018-07-201-2/+0
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| * | clang-format and uncomment debugSergiusz Bazanski2018-07-204-45/+39
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| * | Move pthread yield hack into BaseCtxSergiusz Bazanski2018-07-203-10/+14
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| * | Mix-in Deterministic RNG at Context instead of BaseCtxSergiusz Bazanski2018-07-201-2/+2
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| * | Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnr into ↵Sergiusz Bazanski2018-07-2048-825/+754
| |\ \ | | | | | | | | | | | | q3k/lock-2-electric-boogaloo
| * | | Refactor renderer threadSergiusz Bazanski2018-07-202-27/+64
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| * | | WIP.Serge Bazanski2018-07-177-96/+227
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| * | | Add basic external locking, lock from P&RSerge Bazanski2018-07-173-0/+40
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| * | | Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnr into ↵Serge Bazanski2018-07-1725-395/+1211
| |\ \ \ | | | | | | | | | | | | | | | q3k/lock-2-electric-boogaloo
| * \ \ \ Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnr into ↵Serge Bazanski2018-07-1516-313/+810
| |\ \ \ \ | | | | | | | | | | | | | | | | | | q3k/lock-2-electric-boogaloo
| * | | | | Refactor RNG out to separate DeterministicRNG classSerge Bazanski2018-07-141-57/+67
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This well also allow for better lifecycle control over the state of the RNG in the future.
| * | | | | Refactor IdString functionality into IdStringDBSerge Bazanski2018-07-145-27/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This lets us more precisely control the lifetime of IdString databases in contexts/arches.
* | | | | | Add Loc constructorsClifford Wolf2018-07-214-17/+10
| |_|_|_|/ |/| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | | Added driver and users for netsMiodrag Milanovic2018-07-211-0/+8
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* | | | | Merge branch 'router1ng' into 'master'Clifford Wolf2018-07-212-87/+341
|\ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | Router1ng See merge request SymbioticEDA/nextpnr!13
| * | | | | Bugfix in router1: Also bind src_wireClifford Wolf2018-07-211-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | | Add final sanity check in router1Clifford Wolf2018-07-211-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | | Refactoring of router1Clifford Wolf2018-07-212-87/+320
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Use source-sink pairs as jobs, not whole nets - Route nets with smallest slack first - Preserve routes for already routed source-sink pairs - Add small incentive for re-using wires Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | | | Map ports to netsMiodrag Milanovic2018-07-211-0/+14
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* | | | | | create io cells out of ascMiodrag Milanovic2018-07-211-0/+27
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* | | | | | add cells that are in default state or no configurationMiodrag Milanovic2018-07-211-0/+40
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